Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

A unified flicker noise model which incorporates both the number fluctuation and the correlated surface mobility fluctuation mechanism is discussed. The latter is attributed to the Coulombic scattering effect of the fluctuating oxide charge. The model has a functional form resembling that of the number fluctuation theory, but at certain bias conditions it may reduce to a form compatible with Hooge's empirical expression. The model can unify the noise data reported in the literature, without making any ad hoc assumption on the noise generation mechanism. Specifically, the model can predict the right magnitude and bias dependence of the empirical Hooge parameter. Simulated flicker noise characteristics obtained with a circuit-simulation-oriented flicker noise model based on the new formulation were compared with experimental noise data. Excellent agreement between the calculations and measurement was observed in both the linear and saturation regions for MOS transistors fabricated by different technologies. The work shows that the flicker noise in MOS transistors can be completely explained by the trap charge fluctuation mechanism, which produces mobile carrier number fluctuation and correlated surface mobility fluctuation. >

A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V/sub t/) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

Threshold voltage model for deep-submicrometer MOSFETs

GaN HEMT reliability

A photoresist-ashing process has been developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features. The ultrafine lines were obtained by calibrated ashing of the lithographically defined features in oxygen plasma. The technique has been successfully used to fabricate MOSFETs with effective channel length as small as 0.15 mu m that show excellent characteristics. An NMOS ring oscillator with 0.2- mu m devices has been fabricated with a room-temperature propagation delay of 22 ps/stage. Studies indicate that the thinning is both reproducible and uniform so that it should be usable in circuit as well as device fabrication. Since most polymer-based resist materials are etchable with an oxygen plasma, the basic technique could be extended to supplement other lithographic processes, including e-beam and X-ray processes, for fabricating both silicon and nonsilicon devices and circuits. >

Deep-submicrometer MOS device fabrication using a photoresist-ashing technique

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L/sub eff/=0.15 mu m and T/sub ox/=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO/sub 2/ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 mu m) and oxide thicknesses. >

Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

A comprehensive study of hot-electron-induced substrate and gate currents in deep-submicrometer MOSFETs is presented. The substrate- and gate-current characteristics for devices with channel lengths as small as 0.2 mu m and oxide thickness as thin as 55 AA are examined. Implications for MOSFET reliability and EPROM programming are discussed. In the deep-submicrometer regime, established hot-electron concepts and models are found to be applicable; however, consideration of the finite depth of the current path and current-crowding-induced weak gain control becomes much more important. With these modifications, physical analytical models for substrate and gate currents are developed and verified for deep-submicrometer devices. >

Hot-electron currents in deep-submicrometer MOSFETs

Significant error in the extracted intrinsic transconductance g/sub mi/ can arise from source-drain resistance asymmetry. A simple procedure to either correct for or avoid this source of error is outlined. Using deep-submicrometer devices, experimental results that demonstrate the severity of the potential error and to verify the applicability of the proposed technique are presented. A method which extracts the individual values of the source and drain resistances is also described. >

Intrinsic transconductance extraction for deep-submicrometer MOSFETs

A comprehensive study of the performance and reliability constraints on the dimensions and power supply of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs is presented. Design guidelines extracted from experimental results are presented that are based on the following factors: short-channel effects; drain-induced barrier-lowering effects, off-state leakage currents, hot-electron reliability, time-dependent dielectric breakdown, current-driving capability, voltage gain, and switching speed. The relative importance of each mechanism for a given technology and design is examined. As an example, a set of design curves using typical performance and reliability criteria is provided for n-channel deep-submicrometer devices. With slight modifications, these design curves can also be extended to other technologies, including p-channel and LDD devices. >

M. Jeng

Papers

Deep-submicrometer MOS device fabrication using a photoresist-ashing technique

Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

Hot-electron currents in deep-submicrometer MOSFETs

Intrinsic transconductance extraction for deep-submicrometer MOSFETs

Design guidelines for deep-submicrometer MOSFETs