Journal ArticleDOI
Deep-submicrometer MOS device fabrication using a photoresist-ashing technique
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TLDR
In this paper, a photoresist-ashing process was developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features.Abstract:
A photoresist-ashing process has been developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features. The ultrafine lines were obtained by calibrated ashing of the lithographically defined features in oxygen plasma. The technique has been successfully used to fabricate MOSFETs with effective channel length as small as 0.15 mu m that show excellent characteristics. An NMOS ring oscillator with 0.2- mu m devices has been fabricated with a room-temperature propagation delay of 22 ps/stage. Studies indicate that the thinning is both reproducible and uniform so that it should be usable in circuit as well as device fabrication. Since most polymer-based resist materials are etchable with an oxygen plasma, the basic technique could be extended to supplement other lithographic processes, including e-beam and X-ray processes, for fabricating both silicon and nonsilicon devices and circuits. >read more
Citations
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Journal ArticleDOI
A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors
TL;DR: In this paper, a unified flicker noise model which incorporates both the number fluctuation and the correlated surface mobility fluctuation mechanism is discussed, which can unify the noise data reported in the literature, without making any ad hoc assumption on the noise generation mechanism.
Journal ArticleDOI
Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI
TL;DR: In this article, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases, the voltage drops resulting in a much higher current drive than standard MOSFET for low power supply voltages.
Journal ArticleDOI
Threshold voltage model for deep-submicrometer MOSFETs
TL;DR: In this article, the threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep submicrometer range has been investigated.
Proceedings ArticleDOI
A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation
TL;DR: In this paper, a dynamic threshold voltage MOSFET (DTMOS) was proposed to extend the lower bound of power supply to ultra-low voltages (06 V and below).
Journal ArticleDOI
1.5 nm direct-tunneling gate oxide Si MOSFET's
Hiroki Sasaki,Mizuki Ono,Takashi Yoshitomi,Tatsuya Ohguro,S. Nakamura,Masanobu Saito,Hiroshi Iwai +6 more
TL;DR: In this paper, a 1.5 nm direct-tunneling gate oxide was used to achieve a transconductance of more than 1,000 mS/mm at a gate length of 0.09 /spl mu/m at room temperature.
References
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Journal ArticleDOI
A capacitance method to determine channel lengths for conventional and LDD MOSFET's
Bing J. Sheu,P.K. Ko +1 more
TL;DR: In this article, a simple method for determining the channel length and in situ gate-oxide thickness of MOSFETs is described, based on the linear relationship between the intrinsic gate capacitance and effective channel length.
Journal ArticleDOI
A simple method to determine channel widths for conventional and LDD MOSFET's
Bing J. Sheu,P.K. Ko +1 more
TL;DR: In this paper, the channel width and gate-oxide thickness of conventional and LDD MOSFETs are determined based on the linear relationship between the intrinsic gate capacitance and effective channel width.
Proceedings ArticleDOI
The effects of weak gate-to-drain(source) overlap on MOSFET characteristics
TL;DR: In this article, a simple physical model is presented that adequately explains most of these observed high-field effects, including the asymmetry in device properties, and Implications of the wear-overlap phenomena on future process and device designs are discussed.
Journal ArticleDOI
Sub‐100‐nm channel‐length transistors fabricated using x‐ray lithography
TL;DR: Enhancement mode n-channel Si field effect transistors with channel lengths ranging from 60 nm to 5 μm have been fabricated using combined optical and x-ray lithographies, and were characterized from room temperature to 4.2 K as discussed by the authors.
Journal ArticleDOI
High-speed low-power circuits fabricated using a submicron NMOS technology
Wolfgang Fichtner,E.A. Hofstatter,R.K. Watts,R.J. Bayruns,P.F. Bechtold,R.L. Johnston,D.M. Boulin +6 more
TL;DR: These results illustrate the electrical behavior of single minimum-size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3-GHz divide-by-two counter and a 90- MHz 16 × 16 multiplier.