It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

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High-speed CMOS circuit technique

: This report is addressed to all SPICE2 users involved in the design of MOS (Metal Oxide Semiconductor) IC's (Integrated circuits). The material contained herein serves as an addition to the SPICE2.G User's Guide. The device and model parameters documented refer to the SPICE2.G release versions from the University of California, Berkeley and obsolete the information contained in the SPICE2 MOS Modeling Handbook which is valid for the SPICE2.D release versions. The impact of MOS IC s in both analog and digital applications as well as the decreasing dimensions of the single transistors enabled by advances in processing have made it necessary to refine the models and to provide more information about each device as it appears on the circuit layout. Associated with each MOSFET is a drain and source-junction sidewall capacitance (which has a different voltage dependence than the bottom of the diffusion) and a parasitic series resistance. These are unique to a certain geometry. At the model level there are effects which become important as the channel length and width go below 10um. A thorough description of all parameters appearing on the element (device) card and model card is contained in Sec. 2. In SPICE2.G there are three different MOS models available to the user. The Level 1 model is the simple Shichman-Hodges model implemented according to Nagel s SPICE2: A Computer Program to Simulate Semiconductor Circuits. This first order model has been found necessary for checking out the correctness of hand calculations when understanding or developing new circuits. The Level 2 model is an analytical one-dimensional model which incorporates most of the second-order effects of small-size devices. The Level 3 model is a semi-empirical model described by a set of parameters which are defined by curve-fitting rather than physical background.

/pdf/the-simulation-of-mos-integrated-circuits-using-spice2-23aput6sm0.pdf

The Simulation of MOS Integrated Circuits Using SPICE2

The goals and constraints of MOSFET scaling are reviewed, and the role of reliability constraints is highlighted. It is concluded that judicial shrinking of MOSFET device dimensions can sustain the historical trend of scaling through the 0.09- mu m (4-Gb SRAM) generation of technology, which may be used for IC production in the year 2010. Power supply voltage reduction plus the desire for large transistor current will create a demand for ever thinner gate oxides that can withstand ever higher electric field. Built-in reliability must replace the traditional end-of-the-line reliability testing for future complex circuits. Circuit reliability simulation may be one of the necessary tools for achieving built-in reliability. >

Future CMOS scaling and reliability

We consider the feasibility of fabricating planar superconductor‐semiconductor‐superconductor Josephson junctions in which the junction supercurrent is controlled by a gate electrode isolated from the junction by either a dielectric film (MOS‐JOFET) or a Schottky barrier (MES‐JOFET). We find that device critical currents between ∼1 and 100 μA and critical temperatures approximately a few K appear possible. We discuss the circuit applications of such devices.

Feasibility of hybrid Josephson field effect transistors

A new short-channel threshold voltage model based on an analytic solution of the two-dimensional Poisson equation in the depletion region under the gate of an MOS transistor (MOSTs) is presented. A simple closed-form expression for the variation of threshold voltage as a function of drain voltage, substrate bias, channel length, oxide thickness, and channel doping is derived. An exponential dependence on channel length and a linear dependence on drain and substrate biases is prediced for the reduction in the short-channel threshold voltage. These results are in qualitative and quantitative agreement with simulated and experimental results reported in literature. The predictions for the threshold voltage and subthreshold drain current are in close agreement with measured characteristics of MOS transistors down to submicron dimensions. The closed-form expressions for the threshold voltage and subthreshold drain current are well suited for circuit simulation and for determining performance limits of MOSTs.

Short-channel MOST threshold voltage model

Practical limitations of minimum-size MOS-LSI devices are investigated through measurement of experimental devices. It is assumed that scaled-down MOSFET's are limited by three physical phenomena. These are 1) poor threshold control which is caused by drain electric field, 2) reduced drain breakdown voltage due to lateral bipolar effects, and 3) hot-electron injection into the gate oxide film which yields performance variations during device operation. Experimental models of these phenomena are proposed and the smallest possible MOSFET structure, for a given supply voltage, is considered. It is concluded that the smallest feasible device has a channel length of 0.52 µm and a gate oxide thickness of 9.4 nm when the supply voltage is 1.5 V. Reliable threshold control is most difficult to realize in an MOS-LSI with the smallest devices.

M. Kubo

Papers

Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect