An analyte monitor includes a sensor, a sensor control unit, and a display unit. The sensor has, for example, a substrate, a recessed channel formed in the substrate, and conductive material disposed in the recessed channel to form a working electrode. The sensor control unit typically has a housing adapted for placement on skin and is adapted to receive a portion of an electrochemical sensor. The sensor control unit also includes two or more conductive contacts disposed on the housing and configured for coupling to two or more contact pads on the sensor. A transmitter is disposed in the housing and coupled to the plurality of conductive contacts for transmitting data obtained using the sensor. The display unit has a receiver for receiving data transmitted by the transmitter of the sensor control unit and a display coupled to the receiver for displaying an indication of a level of an analyte. The analyte monitor may also be part of a drug delivery system to alter the level of the analyte based on the data obtained using the sensor.

Analyte Monitoring Device And Methods Of Use

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

CMOS image sensors: electronic camera-on-a-chip

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

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High-speed CMOS circuit technique

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most important advantages of CMOS image sensors over CCDs is the ability to integrate sensing with analog and digital processing down to the pixel level. Finally, we focus on recent developments and future research directions that are enabled by pixel-level processing, the applications of which promise to further improve CMOS image sensor performance and broaden their applicability beyond current markets.

CMOS image sensors

Practical limitations of minimum-size MOS-LSI devices are investigated through measurement of experimental devices. It is assumed that scaled-down MOSFET's are limited by three physical phenomena. These are 1) poor threshold control which is caused by drain electric field, 2) reduced drain breakdown voltage due to lateral bipolar effects, and 3) hot-electron injection into the gate oxide film which yields performance variations during device operation. Experimental models of these phenomena are proposed and the smallest possible MOSFET structure, for a given supply voltage, is considered. It is concluded that the smallest feasible device has a channel length of 0.52 µm and a gate oxide thickness of 9.4 nm when the supply voltage is 1.5 V. Reliable threshold control is most difficult to realize in an MOS-LSI with the smallest devices.

Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect

The development of a high-sensitivity 320 × 244 element MOS area sensor and a novel fixed pattern noise (FPN) suppressing circuit are reported in this paper. The new device incorporates p+-n+high-C photodiodes and double-diffused sense lines. The p+-n+high- C photodiodes provide a large dynamic range and a large saturation signal of 1.4 µA with 6-1x W-lamp illumination. The double-diffused sense lines are introduced to vastly improve blooming characteristics, making use of a built-in potential barrier. FPN is proved to stem mainly from inversion charge variations through horizontal switching MOS gate capacitances. A simple high-performance FPN suppressing circuit is proposed which realizes high signal-to-noise ( S/N ) ratios of more than 68 dB at saturation. The new sensor is tested in a high-sensitivity black-and-white VTR hand-held camera and will find broad applications.

MOS area sensor: Part II&#8212;Low-noise MOS area sensor with antiblooming photodiodes

A protective circuit comprises a metal-oxide-semiconductor field effect transistor (MOSFET) to be protected, and a depletion-type MOSFET the gate and source of which are connected to each other and the souce of which is connected to the gate of the MOSFET to be protected, whereby the protective circuit which is suitable for a high-speed operation is completed.

Protective circuit and device for metal-oxide-semiconductor field effect transistor and method for fabricating the device

An analyzer includes an exchangeable and consumable element such as a sensor, column or reagent the characteristic of which specifies an analyzing condition. The element is provided with a non-volatile semiconductor memory which holds an analyzing condition adapted for the element as data. When the element is mounted on an analyzer body, a controller of the analyzer reads the analyzing condition from the memory to update an analyzing condition inherently provided in the analyzer body. The result of analysis and/or operational history information of use of the element may be written into the memory with which the element is provided.

Analyzer having sensor with memory device

The design considerations and performance of a new MOS imaging device with novel random noise suppression (RANS) circuits are described. This device consists of 492 × 388 photodiodes, a vertical shift register, and a horizontal BCD register integrated in p-wells. The RANS circuits accelerate the charge-transfer speed from vertical signal lines to a horizontal BCD register with 98-percent efficiency. They also decrease the effective signal line capacitance, so noise due to the transfer MOS switches is suppressed to obtain a high signal-to-noise ratio of 46 dB at a standard scene illumination of 180 lx (F1.4) with no image lag and blooming. Sweep out operation for the smear charge accumulated in the vertical signal lines realizes a sufficient signal-to-smear ratio of 69 dB at 1/10 vertical scene illumination.

Masaaki Nakai

Papers

Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect

MOS area sensor: Part II—Low-noise MOS area sensor with antiblooming photodiodes

Protective circuit and device for metal-oxide-semiconductor field effect transistor and method for fabricating the device

Analyzer having sensor with memory device

Design consideration and performance of a new MOS imaging device

Masaaki Nakai

Papers

Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect

MOS area sensor: Part II&#8212;Low-noise MOS area sensor with antiblooming photodiodes

Protective circuit and device for metal-oxide-semiconductor field effect transistor and method for fabricating the device

Analyzer having sensor with memory device

Design consideration and performance of a new MOS imaging device

MOS area sensor: Part II—Low-noise MOS area sensor with antiblooming photodiodes