Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

This paper reviews recent trends in power semiconductor device technology that are leading to improvements in power losses for power electronic systems. In the case of low voltage ( 100 V) power rectifiers, the silicon P-i-N rectifier continues to dominate but significant improvements are expected by the introduction of the silicon MPS rectifier followed by the GaAs and SiC based Schottky rectifiers. Equally important developments are occurring in power switch technology. The silicon bipolar power transistor has been displaced by silicon power MOSFETs in low voltage ( 100 V) systems. The process technology for these MOS-gated devices has shifted from V-MOS in the early 1970s to DMOS in the 1980s, with more recent introduction of the UMOS technology in the 1990s. For the very high power systems, the thyristor and GTO continue to dominate, but significant effort is underway to develop MOS-gated thyristors (MCTs, ESTs, DG-BRTs) to replace them before the turn of the century. Beyond that time frame, it is projected that silicon carbide based switches will begin to displace these silicon devices.

Trends in power semiconductor devices

Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower-trench based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.

Power semiconductor devices having improved high frequency switching and breakdown characteristics

A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

High-breakdown-voltage semiconductor device

An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (f) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.

Trench DMOS transistor with embedded trench schottky rectifier

A trench MOS Schottky barrier rectifier includes a semiconductor substrate having first and second faces, a cathode region of first conductivity type at the first face and a drift region of first conductivity type on the cathode region, extending to the second face. First and second trenches are formed in the drift region at the second face and define a mesa of first conductivity type therebetween. The mesa can be rectangular or circular in shape or of stripe geometry. Insulating regions are defined on the sidewalls of the trenches, adjacent the mesa, and an anode electrode is formed on the insulating regions, and on the top of the mesa at the second face. The anode electrode forms a Schottky rectifying contact with the mesa. The magnitude of reverse-biased leakage currents in the mesa and the susceptibility to reverse breakdown are limited not only by the potential barrier formed by the rectifying contact but also by the potential difference between the mesa and the portion of anode electrode extending along the insulating regions.Moreover, by properly choosing the width of the mesa, and by doping the mesa to a concentration greater than about 1x1016 per cubic centimeters, reverse blocking voltages greater than those of a corresponding parallel-plane P-N junction rectifier can be achieved.

Schottky barrier rectifier with mos trench

Summary form only given The impact of using submicron technology (05- mu m design rules) on JBS (junction barrier controlled Schottky) rectifiers is examined Two-dimensional numerical simulations demonstrate that decreasing P/sup +/-junction width and depth improves the on-state voltage drop This is due to the improved utilization of the active area for the Schottky region and improved spreading of majority carrier current from the Schottky contact However, a junction depth of less than 03 mu m results in an undesirable high electric field at the Schottky interface during reverse bias, leading to barrier height lowering, which produces a large leakage current A large reduction in the spreading resistance is possible by increasing the N-epitaxial layer doping and by reducing the cell pitch in order to achieve the same pinch-off voltage However, increasing the doping above 2*10/sup 16/ cm/sup -3/ reduces the breakdown voltage below 25 V (which is required for 5 V power supplies) The simulations showed that, by using a proper choice of N-doping and P/sup +/-linewidth, one can reduce the leakage by one to two orders of magnitude as compared to a conventional Schottky buried diode Experiments conducted to verify the simulations clearly demonstrate that the use of submicron technology can lead to significant improvement in JBS rectifier characteristics >

Very low forward drop JBS rectifiers fabricated using submicron technology

A new rectifier structure, called Trench MOS Barrier Schottky (TMBS) rectifier has been modeled and fabricated with excellent trade-off characteristics. Two-dimensional numerical simulations have demonstrated coupling between the charge in the N/sup -/ drift region and the metal on the trench sidewalls resulting in an improved electric field distribution. For epitaxial layer doping of 1/spl times/10/sup 17/ cm/sup -3/, simulations show that breakdown voltages of three times the plane parallel breakdown can be achieved with low leakage current. The measured forward drops for the 0.5 /spl mu/m devices at 60 A/cm/sup 2/ and 300 A/cm/sup 2/ were 0.2 V and 0.28 V respectively. Due to smaller drift region resistances, TMBS rectifiers can be operated at large current densities (/spl ap/300 A/cm/sup 2/) resulting in small device sizes. >

The trench MOS barrier Schottky (TMBS) rectifier

A comparative analysis of the p-i-n, SSD (static shielding diode), SFD (soft and fast recovery diode), SPEED (self-adapting P-emitter efficiency diode), and MPS (merged P-N Schottky) rectifiers is performed using the two-dimensional numerical simulator MEDICI. Identical drift region properties are used to obtain the forward I-V, reverse I-V, and reverse recovery characteristics. The MPS, SSD, and SFD rectifiers are found to exhibit a much smaller stored charge and a shorter reverse recovery time than the other rectifiers. As the dose and depth of the shallow P-region implant is increased, the SSD rectifier characteristics are found to shift from those of the MOS rectifier to those of the p-i-n rectifier. It is concluded that the tradeoff between stored charge, leakage current, reverse recovery time, and forward voltage drop is best for the MPS and SSD rectifiers. These rectifiers also exhibit improved soft recovery during switching. >

M. Mehrotra

Papers

Schottky barrier rectifier with mos trench

Very low forward drop JBS rectifiers fabricated using submicron technology

The trench MOS barrier Schottky (TMBS) rectifier

Comparison of high voltage rectifier structures

Schottky-gleichrichter mit mos-gräben