In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

This paper considers externally linear, time-invariant systems which can be internally nonlinear and/or time-varying. Several examples of the synthesis of such systems are presented, and it is argued that they offer advantages in comparison to internally linear, time-invariant systems. In particular, their use in signal processing is considered, and it is shown that they can be designed to reduce the undesirable effects of overloading and noise corruption through the use of companding. It is shown that a variety of previously proposed schemes for this purpose are all related. Several practical problems are discussed, as are performance criteria and types of measurements needed for the evaluation of the systems discussed.

Externally linear, time-invariant systems and their application to companding signal processors

This chapter covers device and circuit aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. Low-current biasing also has a strong influence on noise and matching properties. All these issues are discussed, together with the particular aspects related to passive devices and parasitic effects. The design process has to be supported by efficient and accurate circuit simulation. To this end, the EKV compact MOST model for circuit simulation is presented. The use of the basic concepts such as pinch-off voltage, inversion factor and specific current are highlighted thanks to some very simple but fundamental circuits and to an effective use of the model. New design techniques that are appropriate for low-power and/or low-voltage circuits are presented with an emphasis on the analog floating point technique, the instantaneous companding principle, and their application to filters.

CMOS low-power analog circuit design

A fourth-order low-pass continuous-time filter for a UMTS/WLAN receiver of a reconfigurable terminal is presented. The filter uses the cascade of two Active-Gm-RC biquad cells. A single opamp is used for each biquad and its unity-gain-bandwidth is comparable to the filter cut-off frequency. Thus, the opamp power consumption is strongly reduced w.r.t. other closed-loop filter configurations. The cut-off frequency deviation due to the technological spread, aging and temperature variation is adjusted by an on-chip tuning circuit. The device in a 0.13 mum CMOS technology occupies a 0.9 mm2 area and it consumes 3.4 mW and 11 4.2 mW for the UMTS and WLAN, respectively. The full chip has been designed using an automatic design tool, which is validated by the agreement between the experimental results and the expected performance

A 4th-order active-G/sub m/-RC reconfigurable (UMTS/WLAN) filter

New structures of differential and single-ended log-domain integrators are proposed, which can be used for very low supply voltage continuous-time filters. They offer a tuning range of several decades and operate at minimum supply voltages down to 1 V. The single-ended version allows very simple filter structures, whereas the differential one can be driven by signal currents which are much larger than the bias currents (class AB operation).

A new 1.2 V BiCMOS log-domain integrator for companding current-mode filters

This paper presents the most important properties of log-domain filters for the realization of low-voltage and low power analog signal processing circuits. The noise behavior is discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and CMOS realizations operating at supply voltages as low as 1 V are presented.

Low-voltage log-domain signal processing in CMOS and BiCMOS

A family of differential companding current-mode integrators is proposed, which can be used as building blocks for high frequency continuous-time filters. They offer a tuning range of several decades and can be driven by signal currents which are much larger than the biasing currents (class AB operation). The minimum supply voltage ranges from 1.8 V down to 1 V, depending on the circuit architecture.

Low-voltage companding current-mode integrators

Companding improves dynamic range in situations with restricted signal swing, such as in low-voltage circuits, without the need to reduce noise at the cost of increased power dissipation. The log-domain filter principle achieves instantaneous signal companding by taking advantage of exponential device characteristics. Thanks to the high compression ratio, voltage swing and frequency tuning become almost independent of supply voltage, which can be reduced to the minimum required for proper operation. The combination of instantaneous companding with class AB operation permits processing of signals much larger than the bias level and hence increases dynamic range substantially. Class AB log-domain filters are suited to low-voltage and low power applications with moderate signal-to-noise ratio (SNR) and linearity requirements. The authors present a 3/sup rd/-order Chebyshev filter which is based on an integrator and implemented in a 1 /spl mu/m BiCMOS process. The filter can be tuned over more than 3 decades with cut-off frequencies ranging from 10 kHz to 15 MHz at supply voltages between 0.9 V and 2 V. For a 1.2 V supply, cut-off frequencies up to about 1 MHz are achieved.

A 1.2 V BiCMOS class AB log-domain filter

The noise performance of instantaneous companding filters in the presence of a low frequency input signal is investigated. Log-domain integrators are taken as examples for more detailed considerations. The results are extended to a 3rd-order Chebyshev filter and are in good agreement with measurements of a BiCMOS implementation.

M. Punzenberger

Papers

A new 1.2 V BiCMOS log-domain integrator for companding current-mode filters

Low-voltage log-domain signal processing in CMOS and BiCMOS

Low-voltage companding current-mode integrators

A 1.2 V BiCMOS class AB log-domain filter

Noise in instantaneous companding filters