This paper presents a CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC. Like the well-known column-level single-slope ADC, an MRSS ADC uses a very simple analog column circuit, which mainly consists of an analog comparator and some switches. A prototype imager using the MRSS ADC architecture was realized in a 0.25 CMOS process. Measurements demonstrate that the conversion speed of an MRSS ADC is 3.3 higher than a single-slope ADC while dissipating only 16% more power. Furthermore, the MRSS ADC can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals. Measurements show that the resulting multiple-ramp multiple-slope ADC is 25% faster than an MRSS ADC while dissipating the same amount of power.

Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors

Over the last decade, CMOS image sensor technology made huge progress. Not only the performance of the imagers was drastically improved, but also their commercial success boomed after the introduction of mobile phones with an onboard camera. Many scientists and marketing specialists predicted 15 years ago that CMOS image sensors were going to completely take over from CCD imagers, in the same way as CCD imagers did mid eighties when they took over the imaging business from tubes [1]. Although CMOS has a strong position in imaging today, it did not rule out the business of CCDs. On the other hand, the CMOS-push drastically increased the overall imaging market due to the fact that CMOS image sensors created new application areas and they boosted the performance of CCD imagers as well. This paper describes the state-of-the-art of CMOS image sensors as well as the future perspectives.

/pdf/cmos-image-sensors-state-of-the-art-and-future-perspectives-2u79bdtlwd.pdf

CMOS image sensors: State-of-the-art and future perspectives

Recently, the demands to achieve both high-speed and high-quality imaging — including high A/D resolution — have increased The new target specification is 60fps Ultra-High-Definition with 12b resolution This imaging requires 24Gb/s, while reported CMOS image sensors have reached up to 65Gb/s [1–4] This paper presents a 348Gb/s CMOS image sensor with high image quality, which realizes 177M pixels at 120fps with 12b resolution and a dynamic range of over 75dB (one of the highest image qualities, compared with data from [2]) Generally there exists a trade-off between high-speed imaging and high image quality This is because high-speed imaging brings high power with high thermal noise, which also degrades the signal quality, and because fast data transfer may require more output pins, bringing more interference

A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout

A solid state imaging device includes a substrate of a first conductivity type. A transistor, which includes a first gate electrode and a first and second impurity areas, is provided on a surface of the substrate. The first and second impurity areas are formed in the surface of the substrate and sandwich a region under the first gate electrode. A third impurity area of a second conductivity type is formed in the surface of the substrate and spaced from the second impurity area at an opposite side to the first gate electrode. A fourth impurity area is formed under the second impurity area and connected to the third impurity area. A second gate electrode is provided above the substrate. A fifth impurity area of the second conductivity type is formed in the surface of the substrate. The third and fifth impurity areas sandwich a region under the second gate electrode.

Solid state imaging device

This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. A prototype sensor comprising 640 $\times$ 480 pixels was fabricated with a 0.13- $\mu{\rm m}$ CMOS process. The results of experiments conducted indicate that the proposed ADC can achieve a conversion time of 6.4 $\mu{\rm s}$ at a main clock frequency of 62.5 MHz, which is 10.2 times faster than the conventional SS ADC. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). Further, the proposed circuit employs redundancy error correction logic to calibrate the error between the coarse and fine steps. The total power consumption is 72 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital). The figure of merit (FoM) of the proposed VGA CMOS image sensor is 2.01 $[e^{-}\ {\rm nJ}]$ .

High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs

A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.

M.R. Snoeij

Papers

A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC