Proceedings ArticleDOI
A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC
M.R. Snoeij,P. Donegan,Albert J. P. Theuwissen,Kofi A. A. Makinwa,Johan H. Huijsing +4 more
- pp 506-618
TLDR
A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture that has a 3.3times shorter conversion time than classic single-Slope architecture with equal power.Abstract:
A CMOS image sensor uses a column-level ADC with a multiple-ramp single-slope (MRSS) architecture. This architecture has a 3.3times shorter conversion time than classic single-slope architecture with equal power. Like the single-slope ADC, the MRSS ADC requires a single comparator per column, and, additionally, 8 switches and some digital circuitry. A prototype in a 0.25mum CMOS process has a frame rate 2.8times that of a single-slope ADC while dissipating 24% more power.read more
Citations
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Journal ArticleDOI
Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors
TL;DR: A CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC that can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals.
Proceedings ArticleDOI
CMOS image sensors: State-of-the-art and future perspectives
TL;DR: The state-of-the-art of CMOS image sensors as well as the future perspectives are described.
Proceedings ArticleDOI
A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout
Takayuki Toyama,Koji Mishina,Hiroyuki Tsuchiya,Tatsuya Ichikawa,Hiroyuki Iwaki,Yuji Gendai,Hirotaka Murakami,Kenichi Takamiya,Hiroshi Shiroshita,Yoshinori Muramatsu,Toshihiro Furusawa +10 more
TL;DR: This paper presents a 34.8Gb/s CMOS image sensor with high image quality, which realizes 17.7M pixels at 120fps with 12b resolution and a dynamic range of over 75dB (one of the highest image qualities, compared with data from [2]).
Patent
Solid state imaging device
TL;DR: In this article, the first and second impurity areas are formed in the surface of the substrate and sandwich a region under the first gate electrode, and a third impurity area of a second conductivity type is formed on the substrate.
Journal ArticleDOI
High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs
TL;DR: This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors and employs redundancy error correction logic to calibrate the error between the coarse and fine steps.
References
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Proceedings ArticleDOI
High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor
Y. Nitta,Yoshinori Muramatsu,K. Amano,Takayuki Toyama,JunYamamoto,Koji Mishina,A. Suzuki,T. Taura,Akihiko Kato,M. Kikuchi,Y. Yasui,H. Nomura,Noriyuki Fukushima +12 more
TL;DR: A progressive 1/1.8-inch 1920times1440 CMOS image sensor with a column-inline dual CDS architecture uses a 0.18mum CMOS process that implements digital double sampling with analog CDS on a column parallel ADC.
Proceedings ArticleDOI
A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction
Tadashi Sugiki,Shinji Ohsawa,Hiroki Miura,Michio Sasaki,Nobuo Nakamura,I. Inoue,M. Hoshino,Y. Tomizawa,T. Arakawa +8 more
TL;DR: In this paper, a 60 mW 10b 660(H)/spl times/490(v) pixel digital CMOS image sensor with column-to-column FPN reduction introduces the double inverting amplifier with double clamp circuit.
Proceedings ArticleDOI
A trimless 16b digital potentiometer
TL;DR: In this paper, a voltage-segment DAC structure implemented in an N-well CMOS bipolar process by potentiometrically buffering a cascaded second stage across adjacent taps of an untrimmed resistor string is presented.