This work is a contribution to a drastic change in standard signal processing chains. The main objective is to reduce the power consumption by one or two orders of magnitude. Integrated Smart Devices and Communicating Objects are application domains targeted by this work. In this context, we present a new class of Analog-to-Digital Converters (ADCs), based on an irregular sampling of the analog signal, and an asynchronous design. Because they are not conventional, a complete design methodology is presented. It determines their characteristics given the required effective number of bits and the analog signal properties. it is shown that our approach leads to a significant reduction in terms of hardware complexity and power consumption. A prototype has been designed for speech applications, using the STMicroelectronics 0.18-/spl mu/m CMOS technology. Electrical simulations prove that the factor of merit is increased by more than one order of magnitude compared to synchronous Nyquist ADCs.

A new class of asynchronous A/D converters based on time quantization

This paper describes a new generation of contactless smart card chip which integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit microcontroller. Beyond the contactless smart card application field, this new chip demonstrates that system-on-chip integrating power reception and management, radio-frequency communication, and signal processing is feasible. It associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS six metal layers 0.25-/spl mu/m technology from STMicroelectronics.

A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller

We propose link structures for NoC that have properties for tolerating efficiently transient, intermittent, and permanent errors. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. The protection against transient errors is realized using Hamming coding and interleaving for error detection and retransmission as the recovery method. We introduce two approaches for tackling the intermittent and permanent errors. In the first approach, spare wires are introduced together with reconfiguration circuitry. The other approach uses time redundancy, the transmission is split into two parts, where the data is doubled. In both structures the presence of permanent or intermittent errors is monitored by analyzing previous error syndromes. The links are based on self-timed signaling in which the handshake signals are protected using triple modular redundancy. We present the structures, operation, and designs for the different components
of the links. The fault tolerance properties are analyzed using a fault model containing temporary, intermittent, and permanent faults that occur both as bursts and as single faults. The results show a considerable enhancement in the fault tolerance at the cost of performance and area, and with only a slight increase in power consumption.

/pdf/online-reconfigurable-self-timed-links-for-fault-tolerant-1c2cv13r7d.pdf

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.

/pdf/logic-soft-errors-in-sub-65nm-technologies-design-and-cad-10erdejvq0.pdf

Logic soft errors in sub-65nm technologies design and CAD challenges

This paper is a contribution to the definition of a new kind of digital signal processing chain. It is focused on Finite-Impulse-Response filtering (FIR) applied to irregularly sampled signals obtained from an asynchronous analog to digital converter. The paper first formalizes the convolution operator in the irregular sampling context. The computational complexity is deduced and compared to the one of standard synchronous FIR filters. It shows that a significant reduction of the computational complexity is achievable, hence a reduction in terms of energy. The paper then describes the architecture of the asynchronous filter. It finally reports the simulations performed on a speech application, resulting in a reduction of the processing power of about one order of magnitude.

M. Renaudin

Papers

Asynchronous circuits and systems: a promising design alternative