VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

Tileable field-programmable gate array architecture

We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affecting the programmable switches that configure the FPGA interconnect. As a result, the BIST technique provides complete testing of interconnect faults.

Built-in self-test of FPGA interconnect

Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

Testing the interconnect of RAM-based FPGAs

This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic test configurations to fully test the whole matrix of CLBs. In the proposed test configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of test configurations 8 is fixed and independent of the FPGA size.

RAM-based FPGA's: a test approach for the configurable logic

The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by reprogramming the FPGA during testing, forces a strategy to reduce the number of different configurations used for testing purposes. After finding the optimal solutions for the elementary structures of the Logic block, Multiplexers and Look-Up Tables, the problem of testing interconnected elementary structures is addressed. The method is illustrated using an elementary structure and then applied to a popular FPGA (XILINX 3000 family) where a reduced set of configurations (5) and their corresponding test sequences is found to cover all (100%) the Configurable Logic Block faults modelled.

Test pattern and test configuration generation methodology for the logic of RAM-based FPGA

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach is applied to the XILINX SPARTAN, 4000 and 3000 families. On these examples of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then for a single logic cell, and finally for the m/spl times/m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a single logic cell. An approach is then described to define a minimum number of test configurations for a logic cell knowing the test configurations of its logic modules. This approach gives only 4 test configurations for the XILINX Spartan, 5 for the 4000 and 4 for the 3000 while the previous published works concerning Boolean testing of these FPGA families give 8 for the 4000 and 5 for the 3000.

Minimizing the number of test configurations for different FPGA families

The objective of this paper is to generate an application-oriented test procedure to be used by a FPGA user in a given application General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault' Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description

Analyzing the test generation problem for an application-oriented test of FPGAs

The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. In usual SRAM-based FPGAs, Configurable Interface Modules (CIMs) can be found between the global interconnect and inputs of the logic cells (input CIMs) or between output of the logic cells and the global interconnect (output CIMs). It is demonstrated that an input CIM that connects N/sup in/ segments to a logic cell input requires N/sup in/ test configurations and that an output CIM that connects a logic cell output to N/sup out/ segments requires 2 test configurations. Then, it is proven that a set of K/sup in/ input CIMs can be tested in parallel making the number of required test configurations equal to N/sup in/. In the same way, a set of K/sup out/ output CIMs is shown to require only 2 test configurations if N/sup out/>K/sup out/. Finally, it is shown that the complete mXm array of logic cells with K/sup in/ input CIMs and K/sup out/ output CIMs can be tested with only N/sup in/ test configurations using the XOR tree and shift register structures.

M. Renovell

Papers

RAM-based FPGA's: a test approach for the configurable logic

Test pattern and test configuration generation methodology for the logic of RAM-based FPGA

Minimizing the number of test configurations for different FPGA families

Analyzing the test generation problem for an application-oriented test of FPGAs

Testing the configurable interconnect/logic interface of SRAM-based FPGA's