M
M. S. Hrishikesh
Researcher at University of Texas at Austin
Publications - 4
Citations - 1083
M. S. Hrishikesh is an academic researcher from University of Texas at Austin. The author has contributed to research in topics: Pipeline (computing) & Clock rate. The author has an hindex of 4, co-authored 4 publications receiving 1077 citations.
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Proceedings ArticleDOI
Clock rate versus IPC: the end of the road for conventional microarchitectures
TL;DR: This paper describes technology-driven models for wire capacitance wire delay, and microarchitectural component delay and finds that no scaling strategy permits annual performance improvements of better than 12.5% which is far worse than the annual 50-60% to which the authors have grown accustomed.
Journal ArticleDOI
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
M. S. Hrishikesh,Doug Burger,Norman P. Jouppi,Stephen W. Keckler,Keith Farkas,Premkishore Shivakumar +5 more
TL;DR: This study indicates that further pipelining can at best improve performance of integer programs by a factor of 2 over current designs, and proposes and evaluates a high-frequency design called a segmented instruction window.
Journal ArticleDOI
Static energy reduction techniques for microprocessor caches
TL;DR: This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches and investigates the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.
Proceedings ArticleDOI
A wire-delay scalable microprocessor architecture for high performance systems
Stephen W. Keckler,Doug Burger,Charles R. Moore,Ramadass Nagarajan,Karthikeyan Sankaralingam,Vikas Agarwal,M. S. Hrishikesh,Nitya Ranganathan,Premkishore Shivakumar +8 more
TL;DR: This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays.