Premkishore Shivakumar

TL;DR: An end-to-end model is described and validated that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs and predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SERper chip of unprotected memory elements.

TL;DR: This study indicates that further pipelining can at best improve performance of integer programs by a factor of 2 over current designs, and proposes and evaluates a high-frequency design called a segmented instruction window.

TL;DR: This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution and describes each of the five types of reused tiles that compose the processor, the control and data networks that connect them, and the distributedmicroarchitectural protocols that implement instruction fetch, execution, flush, and commit.

TL;DR: A new yield metric called performance averaged yield (Ypav) is introduced which accounts both for fully functional chips and those that exhibit some performance degradation, and is able to increase the Ypav of a uniprocessor with only redundant rows in its caches from a base value of 85% to 98% using microarchitectural redundancy.

TL;DR: The TRIPS chip prototypes two networks on chip to demonstrate the viability of a routed interconnection fabric for memory and operand traffic and shows that NoCs are area- and complexity-efficient means of providing high-bandwidth, low-latency on-chip communication.