The normal and reverse short-channel effect of LDD MOSFET's with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict V/sub th/ as a function of L/sub eff/, V/sub DS/, V/sub BS/, and pocket parameters down to 0.1-/spl mu/m channel length. The new model shows that the V/sub th/ roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (N/sub p/)/sup 1/4 /L/sub p/. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length L/sub min/ is presented. The theoretical optimal pocket implant performance is to achieve an L/sub min/ approximately 55/spl sim/60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed.

Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's

A semi-empirical analytical model for the DC characteristics of both n- and p-channel polysilicon thin-film transistors is described. The model is suitable for implementation in a SPICE circuit simulator. Our semi-empirical approach results in a physically based model with a minimum of parameters, which are readily related to the device structure and fabrication process. The intrinsic DC model describes all four regimes of operation: leakage, subthreshold, above threshold, and kink. The effects of temperature and channel length are also included in the short-channel model.

A short-channel DC SPICE model for polysilicon thin-film transistors including temperature effects

We present a physically based continuous analytical MOSFET model for submicrometer devices that includes polysilicon depletion effect. It is shown that simple modification to standard MOSFET circuit models is all that is needed to account for the polydepletion effect. The new model accurately predicts, both measured and 2-D simulated, I-V, and C-V characteristics of submicrometer MOSFET's with polydepletion effect over a range of polysilicon gate concentration, N/sub p/, down to 5/spl times/10/sup 18/ cm/sup 3/. It is found that neglecting the polydepletion effect for devices with nondegenerate gate doping leads to nonphysical model parameters and causes large errors in the capacitance modeled results. The new model has been implemented in the circuit simulator SPICE. Since both device current and capacitance degrade due to polydepletion effect, its impact on circuit performance is studied using inverter type circuits with different loading conditions. SPICE simulations show that for 0.35 /spl mu/m CMOS technology (gate oxide thickness, t/sub ox/=70 /spl Aring/) the increase in the delay time for chain of inverters is 3.5% for N/sub p/=2/spl times/10/sup 19/ cm/sup -3/ (for both nand p-channel devices) compared to N/sub p/=5/spl times/10/sup 19/, cm/sup -3/. For a given t/sub ox/ and nondegenerate value of N/sub p/, lowering the channel length helps to reduce the polydepletion effect and hence circuit performance degradation. However, reducing the power supply, for low power operation, enhances the polydepletion effect. >

Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit performance

This is the first book dedicated to the next generation of MOSFET models. Addressed to circuit designers with an in-depth treatment that appeals to device specialists, the book presents a fresh view of compact modeling, having completely abandoned the regional modeling approach.

Mosfet Modeling for Circuit Analysis and Design

A review of hot-carrier degradation mechanisms in MOSFETs

A simple, accurate MOSFET substrate current model suitable for a circuit simulator is presented. The effect of substrate bias on substrate current is modeled without introducing additional parameters. The accuracy of this model is demonstrated by its ability to fit the experimental data for both standard and LDD devices with average errors of less than 6%. The new model is compared with the substrate current models reported in the literature. In addition, the temperature dependence of the substrate current in the range of 0-120 degrees C is also modeled. The new model has been implemented in a circuit-level hot-electron reliability simulator, and the results obtained from simulation of an inverter circuit are presented. >

MOSFET substrate current model for circuit simulation

A simple yet accurate semi-empirical analytical model for simulating the anomalous threshold voltage behavior in submicrometer MOSFETs is reported. The increase in the threshold voltage with decreasing channel length has been modeled by assuming a bias-independent, but channel-length-dependent, fixed charge at the source and drain ends. The new model requires two extra parameters in addition to the usual short-channel threshold voltage model parameters. These two parameters represent the magnitude of the fixed charge and the length over which the charge is spread at the source and drain ends. The model shows excellent agreement with the experimental threshold voltage data (within 2%) for submicrometer devices with varying oxide thickness, junction depth, and channel doping concentration. >

M.S. Sharma

Papers

MOSFET substrate current model for circuit simulation

Modeling the anomalous threshold voltage behavior of submicrometer MOSFET's