Showing papers in "IEEE Transactions on Electron Devices in 1991"

Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures. I. Homogeneous transport

Abstract: Monte Carlo simulations of electron transport in seven semiconductors of the diamond and zinc-blende structure (Ge, Si, GaAs, InP, AlAs, InAs, GaP) and some of their alloys (Al/sub x/Ga/sub 1-x/As, In/sub x/Ga/sub 1-x/As, Ga/sub x/In/sub 1-x/P) and hole transport in Si were performed at two lattice temperatures (77 and 300 K). The model uses band structures obtained from local empirical pseudopotential calculations and particle-lattice scattering rates computed from the Fermi golden rule to account for band-structure effects. Intervalley deformation potentials significantly lower than those which have been previously reported are needed to reproduce available experimental data. This is attributed to the more complicated band structures, particularly around the L- and X-symmetry points in most materials. Satisfactory agreement is obtained between Monte Carlo results and some experiments. >

Optimized antireflection coatings for high-efficiency silicon solar cells

Abstract: Antireflection coatings for silicon solar cells have been optimized both theoretically and experimentally for a range of possible situations, such as single-layer and double-layer coatings, and on planar and microgrooved surfaces. The effect of a thin passivating silicon dioxide layer under the coating was also considered. A critical passivating oxide thickness of about 300 AA was found to be important for the design of these coatings. A new half-quarter-wavelength double layer antireflection coating can be achieved with very low reflection if the passivating oxide has to be thicker than this critical thickness. >

Field-emitter arrays for vacuum microelectronics

Abstract: An ongoing program on microfabricated field-emitter arrays has produced a gated field-emitter tip structure with submicrometer dimensions and techniques for fabricating emitter arrays with tip packaging densities of up to 1.5*10/sup 7/ tips/cm/sup 2/. Arrays have been fabricated over areas varying from a few micrometers up to 13 cm in diameter. Very small overall emitter size, materials selection, and rigorous emitter-tip processing procedures have contributed to reducing the potential required for field emission to tens of volts. Emission current densities of up to 100 A/cm/sup 2/ have been achieved with small arrays of tips, and 100-mA total emission is commonly produced with arrays 1 mm in diameter containing 10000 tips. Transconductances of 5.0 mu S per tip have been demonstrated, indicating that 50 S/cm/sup 2/ should be achievable with tip densities of 10/sup 7/ tips/cm/sup 2/. Details of the cathode arrays and a variety of performance characteristics are discussed. >

A three-step method for the de-embedding of high-frequency S-parameter measurements

Abstract: The authors propose a general method of deembedding S-parameter measurements of the device-under-test (DUT) for which typical parasitics associated with probe pads and interconnect-metal lines can be deembedded from the measurement. The DUT is the analog silicon bipolar junction transistor including the pad and interconnects. This method includes the subtraction of the parasitic shunt y-parameters of the on-wafer open calibration pattern as well as the subtraction of the parasitic series z-parameters on the on-wafer open circuit which are taken from measurements of the short and through circuits. It is demonstrated that the calculated power loss for the pad and interconnect parasitics can be comparable to the power consumption of the advanced bipolar transistor at high frequencies (>or=10 GHz). A knowledge of the magnitude and type of parasitic deembedding circuit elements can aid the device engineer in the analysis of the error associated with deembedding. >

Comparison of transformation to low-resistivity phase and agglomeration of TiSi/sub 2/ and CoSi/sub 2/

Abstract: The phase transformation and stability of TiSi/sub 2/ on n/sup +/ diffusions are investigated. Narrower n/sup +/ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi/sub 2/ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi/sub 2/. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi/sub 2/ on n/sup +/ and p/sup +/ diffusions. No linewidth dependence is observed for the transformation from CoSi/sub x/ to CoSi/sub 2/. There is a broad process window from 575 degrees C to 850 degrees C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration. >

Vacuum microelectronics: what's new and exciting

Abstract: It is argued that the key factor required to make vacuum microelectronics successful is closely related to an understanding and control of the physics, materials and microfabrication technology for field emitter arrays (FEAs). The topics discussed are the optimization and theoretical limit of the FEA; thermal stability of the FEA and the mesoscopic FEA; fabrication and materials of FEAs; and characteristics of FEAs. The author examines basic characteristics, limits and capabilities of FEAs from the viewpoint of optimizing the concept of the most current for the least voltage. >

A simple MOSFET model for circuit analysis

Abstract: A simple, general, yet realistic MOSFET model, the nth power law MOSFET model, is introduced. The model can express I-V characteristics of short-channel MOSFETs at least down to 0.25- mu m channel length and of resistance inserted MOSFETs. The model evaluation time is about 1/3 of the evaluation time of the SPICE3 MOS LEVEL3 model. The model parameter extraction is done by solving single variable equations and thus can be done within a second, unlike the fitting procedure with expensive numerical iterations used for the conventional models. The model also permits analytical treatment of circuits in the short-channel region and plays the role of a bridge between complicated MOSFET current characteristics and circuit behavior in the deep-submicrometer region. >

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Abstract: A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed. >

Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's

Abstract: Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible. >

UV-O/sub 3/ and dry-O/sub 2/: Two-step-annealed chemical vapor-deposited Ta/sub 2/O/sub 5/ films for storage dielectrics of 64-Mb DRAMs

Abstract: A capacitor fabrication technique is developed to obtain an extremely thin Ta/sub 2/O/sub 5/ film with an effective SiO/sub 2/ film thickness of 2.8 nm (equivalent to 12 fF/ mu m/sup 2/) for use in a low-power 64-Mb DRAM. A two-step annealing process is used after deposition of the Ta/sub 2/O/sub 5/ film by thermal chemical vapor deposition (CVD). The first step is ozone (O/sub 3/) annealing with ultraviolet light irradiation, which is the most effective means of reducing leakage current. A model for explaining the effectiveness of the UV-O/sub 3/ annealing treatment is proposed. Excited oxygen atoms in the singlet state (/sup 1/D), which are generated selectively in the ozone gas irradiated by a mercury lamp, repair the oxygen vacancies existing in the as-deposited CVD-Ta/sub 2/O/sub 5/ film, resulting in a marked reduction of the film's leakage current. The second step is dry-O/sub 2/ annealing, which reduces the defect density of initial breakdown. Sufficient capacitance can be obtained while maintaining a low leakage current and sufficient step coverage for a 1.5-V supply-voltage 64-Mb DRAM having a high-aspect three-dimensional memory cell. >

A new aspect of mechanical stress effects in scaled MOS devices

Abstract: Deviation in device characteristics due to mechanical stress is investigated experimentally and analytically from the viewpoints of scaling and hot-carrier effects. A stress analysis program, SIMUS (stress analysis program for multilayer structure) 2D/F, which can analyze the stress state of thin multilayer structures such as LSI devices throughout their manufacturing process, was used. In scaled MOS devices, the effect of uniaxial stress is reduced. However, the effect of vertical stress, such as mold stress, becomes a serious problem when the vertical stress causes compressive surface stress. Compressive stress has a serious effect on electron trapping, in SiO/sub 2./ These results provide important guidelines for the manufacture and package design of deep submicrometer devices. >

High-gain lateral bipolar action in a MOSFET structure

Abstract: A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25- mu m base width have been successfully fabricated in a p-well 0.25- mu m bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported. >

Comments on "Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures. II. Submicrometer MOSFETs" [with reply]

Abstract: For pt.I see ibid., vol.38, no.3, p.634-49, March 1991. MOSFETs with channel lengths smaller than 0.25 mu m with substrates of four different semiconductors and one alloy of the diamond and zinc-blende structures (n-channel Ge, Si, GaAs, InP, In/sub 0.53/Ga/sub 0.47/As, and p-channel Si) were simulated at 77 and 300 K with a self-consistent two-dimensional Monte Carlo program. With the exception of the In-based materials, the speed of the devices appears to be largely independent of the semiconductor. This universal behavior results from the similarity among the medium-energy-scale features of the band structures of the cubic semiconductors. Low-energy concepts, such as mobility and effective mass, fail to describe charge transport as carriers populate a larger fraction of the Brillouin zone in these small devices driven at reasonably high biases. The assumptions made, the approximations used, and, in particular, the meaning of the words speed and reasonably mentioned above are discussed. >

A random access photodiode array for intelligent image capture

Abstract: A chip implementing random scan was designed, fabricated, and tested. The chip covers the basic requirements for random access and separation between the sampling and reading processes. In this way, a repeated reading of any pixel at any time can take place. The chip includes an 80*80 matrix of basic cells. Each cell consists of two stages: The first is based on a switch, whereas the second includes a buffer. The chip was fabricated in a 3- mu m CMOS process. It was found to operate functionally. However, the use of a standard process gave rise to the crosstalk phenomenon, which has yet to be overcome. >

An overview of smart power technology

Abstract: The evolution of smart power technology and the impact of this technology on electronic systems are reviewed. After providing a definition of smart power technology, the author describes the key technological developments in power semiconductor devices, namely power MOSFETs and IGBTs (insulated-gate bipolar transistors). These developments are the foundation upon which smart power technology rests. Smart power technology requires the marriage of power device technology with CMOS logic and bipolar analog circuits. The technical challenges involved in combining power handling capability with on-chip regulation of overcurrent, overvoltage, and overtemperature conditions are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies. >

Direct extraction of the AlGaAs/GaAs heterojunction bipolar transistor small-signal equivalent circuit

Abstract: The authors describe a novel, direct technique for determining the small-signal equivalent circuit of a heterojunction bipolar transistor (HBT). The parasitic elements are largely determined from measurements of test structures, reducing the number of elements determined from measurements of the transistor. The intrinsic circuit elements are evaluated from y-parameter data, which are DC-embedded from the known parasitics. The equivalent-circuit elements are uniquely determined at any frequency. The validity of this technique is confirmed by showing the frequency independence of the extracted circuit elements. The equivalent circuit models the HBT s-parameters over a wide range of collector currents. Throughout the entire 1-18-GHz frequency range, the computed s-parameters agree very well with the experimental data. >

An abuttable CCD imager for visible and X-ray focal plane arrays

Abstract: A frame-transfer silicon charge-coupled-device (CCD) imager has been developed that can be closely abutted to other imagers on three sides of the imaging array. It is intended for use in multichip arrays. The device has 420*420 pixels in the imaging and frame-store regions and is constructed using a three-phase triple-polysilicon process. Particular emphasis has been placed on achieving low-noise charge detection for low-light-level imaging in the visible and maximum energy resolution for X-ray spectroscopic applications. Noise levels of 6 electrons at 1-MHz and less than 3 electrons at 100-kHz data rates have been achieved. Imagers have been fabricated on 1000- Omega cm material to maximize quantum efficiency and minimize split events in the soft X-ray regime. >

Impact of the vertical SOI 'DELTA' structure on planar device technology

Abstract: A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance. >

LWIR 128*128 GaAs/AlGaAs multiple quantum well hybrid focal plane array

Abstract: The authors describe the fabrication and performance of a new type of hybrid focal plane array (FPA). The hybrid consists of a 128*128 GaAs/AlGaAs superlattice multiple-quantum-well detector array with peak response at 7.7 mu m mated to a high-performance CMOS readout with direct injection input. The quantum-well infrared photodetector (QWIP) array was fabricated by molecular-beam epitaxy (MBE). Optical gratings were excluded to facilitate evaluation of the basic detector-technology. The mean D* at 78 K was 5.76*10/sup 9/ cm- square root Hz/W. Total FPA 1/f noise was negligible, as corroborated by imagery having minimum resolvable temperature (MRT) of 30 mK at 0.07 cycles/mrad. No gain nonuniformity correction was used in the imaging demonstration. >

Hydrodynamic equations for semiconductors with nonparabolic band structure

Abstract: A system of generalized hydrodynamic equations is derived from Boltzmann's transport equation for semiconductors without the assumption of a parabolic band structure. After some simplifications these equations can be arranged in such a way that their structure is similar to that of the well-known conventional ones. For this purpose the quantity carrier temperature is redefined and five relaxation times have to be introduced instead of the two in use so far, in order to take nonparabolicity into account. For all quantities of interest results from Monte Carlo simulation are presented for silicon with an impurity concentration of up to 10/sup 18/ cm/sup -3/ and an electric field of up to 200 kV/cm. They show that two of the five relaxation times are not distinguishable; hence, for silicon at room temperature the number of relaxation times can be reduced to four. Considerable deviations from results derived under the assumption of a parabolic band structure demonstrate the necessity of this generalized hydrodynamic model. The new hydrodynamic model is applied to a n-channel LDD MOSFET with a 0.5- mu m channel length. The results agree well with the results of Monte Carlo device simulation. >

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Abstract: The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. >

Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters

Abstract: A technique is presented to determine the effective process and design-related parameters from the high-current I-Vcharacteristics of NMOSTs, for use in the development of electrostatic discharge (ESD) protection circuits. Test structures from a fully salicided, LDD MOS process were characterized with a transmission line pulse generator to obtain the snapback voltages and the second-breakdown trigger currents (I/sub t2/) Good correlations are shown between I/sub t2/ and the human body model (HBM) ESD damage thresholds. It was seen that homogeneous current injection in the avalanching diffusions is imperative for good second breakdown behavior. A simplified thermal model, with second breakdown as the boundary condition for damage, was used in the extraction of the effective junction depth, depletion width, and transistor width under high-current conditions. Experimental data obtained for the power-to-failure as a function of the time-to-failure showed a good fit to the model. A possible extension of the technique for the use of DC characterization to monitor ESD behavior is presented. >

Studies of diffused boron emitters: saturation current, bandgap narrowing, and surface recombination velocity

Abstract: The emitter saturation current density, J/sub 0/ was measured on diffused boron emitters in silicon for the case in which the emitter surface is passivated by a thermal oxide and for the case in which Al/Si is deposited on the emitter surface. The oxide-passivated emitters have a surface recombination velocity, s, which is near its lowest technologically achievable value. In contrast, the emitters with Al/Si on the surface have surface recombination velocities which approach the maximum possible value of s. From the J/sub 0/ measurements, the apparent bandgap narrowing as a function of boron doping was found. Using this bandgap narrowing data, the surface recombination velocity at the Si/SiO/sub 2/ interface was extracted for surface boron concentrations from 3*10/sup 17/ to 3*10/sup 19/ cm/sup -3/. >

Emitter ballasting resistor design for, and current handling capability of AlGaAs/GaAs power heterojunction bipolar transistors

Abstract: A systematic investigation of the emitter ballasting resistor for power heterojunction bipolar transistors (HBTs) is presented. The current handling capability of power HBTs is found to improve with ballasting resistance. An equation for the optimal ballasting resistance is presented, where the effects of thermal conductivity of the substrate material and the temperature coefficient of the ballasting resistor are taken into account. Current levels of 400 to 800 mA/mm of emitter periphery at case temperatures of 25 to -80 degrees C for power AlGaAs/GaAs HBTs have been obtained using an on-chip lightly doped GaAs emitter ballasting resistor. Device temperature has been measured using both an infrared microradiometer and temperature-sensitive electrical parameters. Steady-state and transient thermal modeling are also performed. Although the measured temperature is spatially nonuniform, the modeling results show that such nonuniformities would occur for a uniform current distribution, as would be expected for an HBT with emitter ballasting resistors. >

Polysilicon thin-film transistors with channel length and width comparable to or smaller than the grain size of the thin film

Abstract: Poly-Si thin-film transistors (TFTs) with channel dimensions (width W, and length L) comparable to or smaller than the grain size of the poly-Si film were fabricated and characterized. The grain size of the poly-Si film was enhanced by Si ion implantation followed by a low-temperature anneal and was typically 1 to 3 mu m in diameter. A remarkable improvement was observed in the device characteristics as the channel dimensions decreased to W=L=2 mu m. On the other hand, TFTs with submicrometer channel dimensions were characterized by an extremely abrupt switching in their I/sub D/ versus V/sub GS/ characteristics. The improvement was attributed to a reduction in the effect of the grain boundaries and to the effect of the device's floating body. >

Numerical simulation of a steady-state electron shock wave in a submicrometer semiconductor device

Abstract: Appropriate numerical methods for steady-state simulations (including shock waves) when the electron flow is both subsonic and supersonic are addressed. The one-dimensional steady-state hydrodynamic equations will then be elliptic in the subsonic regions and hyperbolic/elliptic in the supersonic regions. A second upwind method is used for both elliptic and hyperbolic/elliptic regions. In the elliptic regions, the second upwind method is related to the Scharfetter-Gummell exponential fitting method. The hydrodynamic model consists of a set of nonlinear conservation laws for particle number, momentum, and energy, coupled to Poisson's equation for the electric potential. The nonlinear conservation laws are just the Euler equations of gas dynamics for a gas of charged particles in an electric field, with the addition of a heat conduction term. Thus the hydrodynamic model partial differential equations (PDEs) have hyperbolic, parabolic, and elliptic modes. The nonlinear hyperbolic modes support shock waves. The first numerical simulations of a steady-state electron shock wave in a semiconductor device are presented, using the hydrodynamic model. For the ballistic diode (which models the channel of a MOSFET), the shock wave is fully developed in Si (with 1-V bias) at 300 K for a 0.1- mu m channel and at 77 K for a 1.0- mu m channel. >

Spectroscopic charge pumping: A new procedure for measuring interface trap distributions on MOS transistors

Abstract: An approach to the application of the charge pumping technique is proposed as a tool for the measurement of interface trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the interface-trap distribution is slowly varying with energy and that the trap capture cross section is nearly constant over energy and temperature. >

Sealed vacuum devices: fluorescent microtip displays

Abstract: Emission uniformity and reliability are critical to the successful application of vacuum microelectronics to flat-panel displays. The authors discuss two techniques that address these issues. The first technique uses a series resistance to limit tip current and the second involves the partitioning of the emitting tips. Used together, they have caused a substantial improvement in current uniformity. A real averaging effect among tips has been achieved by adding a resistive layer. The structure has been hardened to shorts with a hemstitched electrode. These improvements have led to the demonstration of emission homogeneity and stability across a 6-in diagonal substrate. >

Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions

Abstract: The most commonly used high-voltage blocking and termination structures-floating field limiting rings (FLR), lateral charge control HVIC devices, and junction termination extension (JTE) structures-are very sensitive to positive silicon and silicon dioxide interface charges. These high-voltage termination structures specifically designed for 1000-V blocking capability lose 25 to 50% of their voltage-blocking capability under 5*10/sup 11/ cm/sup -2/ net interface state density. In contrast, optimized multiple-zone JTE (MZ-JTE), and offset multiple field plated and field-limiting ring (OFP-FLR) structures will lose only 5% of their respective voltage blocking capabilities under the same surface-charge condition. These improved high-voltage blocking structures do not require additional passivation and process complexities. >