Coefficient multipliers are the stumbling blocks in programmable finite impulse response (FIR) digital filters. As the filter coefficients change either dynamically or periodically, the search for common subexpressions for multiplierless implementation needs to be performed over the entire gamut of integers of the desired precision, and the amount of shifts associated with each identified common subexpression needs to be memorized. The complexity of a quality search is thus beyond the existing design algorithms based on conventional binary and signed digit representations. This paper presents a new design paradigm for the programmable FIR filters by exploiting the extended double base number system (EDBNS). Due to its sparsity and innate abstraction of the sum of binary shifted partial products, the sharing of adders in the time-multiplexed multiple constant multiplication block of the programmable FIR filters can be maximized by a direct mapping from the quasi-minimum EDBNS. The multiplexing cost can be further reduced by merging double base terms. Logic synthesis results on more than one hundred programmable filters with filter taps ranging from 10 to 100 and coefficient word lengths of 8, 12, and 16 bits show that the average logic complexity and critical path delay of the programmable FIR filters designed by our proposed algorithm have been reduced by up to 47.81% and 14.32%, respectively over the existing design methods.

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Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System

This paper presents three optimal-complexity structures (I, II, III) for pipelined distributed arithmetic (DA) based least-mean-square (LMS) adaptive filter The complexity of proposed structures is reduced by implementing offset-binary-coding (OBC) combinations of input samples on hardware However, some non-OBC outputs are produced, and subsequently eliminated in the error computation during the initial clock cycles For achieving more performance benefits, radix-4 OBC combinations of input samples are implemented with the proposed partial product generators In addition, novel low-complexity implementations for the offset term, weight update block and shift-accumulate unit are also proposed Analysis shows that byte-complexity of proposed structures vary linearly with the order of DA base unit, while their bit-complexity depends on the topology All the structures show significant hardware savings, Structure-I has least critical-path and Structure-II, III offer superior convergence performance Experimental results show that the Structure-I, II and III with 32 nd order filter provide savings 7113%, 7183% and 7308% in area, 6847%, 7001% and 7217% in power, 5174%, 3783% and 4538% in area-per-throughput (APT), 4733%, 3372% and 4319% in power-per-throughput (PPT), 5511%, 5966% and 6420% in slice LUTs, 3533%, 4028% and 4487% in flip-flops over the best existing scheme

Optimal Complexity Architectures for Pipelined Distributed Arithmetic-Based LMS Adaptive Filter

The discrete wavelet transform is a fundamental block in several schemes for image compression. Its implementation relies on filters that usually require multiplications leading to a relevant hardware complexity. Distributed arithmetic is a general and effective technique to implement multiplierless filters and has been exploited in the past to implement the discrete wavelet transform as well. This work proposes a general method to implement a discrete wavelet transform architecture based on distributed arithmetic to produce approximate results. The novelty of the proposed method relies on the use of result-biasing techniques (inspired by the ones used in fixed-width multiplier architectures), which cause a very small loss of quality of the compressed image (average loss of 0.11 dB and 0.20 dB in terms of PSNR for the 9/7 and 10/18 wavelet filters, respectively). Compared with previously proposed distributed-arithmetic-based architectures for the computation of the discrete wavelet transform, this technique saves from about 20% to 25% of hardware complexity.

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Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT

In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.

High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

A highly scalable parallel spike-based digital neuromorphic architecture for high-order fir filters using LMS adaptive algorithm

A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate operations on these partial products. In the case of an adaptive filter, it is required that the filter coefficients be updated and, hence, these LUTs are to be recalculated. A new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time. Simulation results show that the proposed scheme consumes very less chip area and operates at high throughput for large base unit size k ( = N/m) , where m is an integer and N is the number of filter coefficients. For example, a 128-tap finite-impulse-response adaptive filter with the proposed implementation produces 12 times more throughput (for k = 8) and consumes almost 26% less area when compared to the best of existing architectures.

Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic

A distributed arithmetic (DA)-based decision feedback equalizer architecture for IEEE 802.11b PHY scenarios is presented. As the transmission data rate increases, the hardware complexity of the decision feedback equalizer increases due to requirement for large number of taps in feed forward and feedback filters. DA, an efficient technique that uses memories for the computation of inner product of two vectors, has been used since DA-based realization of filters can lead to great computational savings. For higher-order filters, the memory-size requirement in DA would be high, and so ROM decomposition has been employed. The speed is further increased by employing digit-serial input operation. Two architectures have been presented, namely the direct-memory architecture and reduced-memory architecture where the later is derived using the former. A third architecture has also been presented where the offset-binary coding scheme is employed along with the ROM decomposition and digit-serial variants of DA. Synthesis results on Altera Cyclone III EP3C55F484C6 FPGA show that the proposed DA-based implementations are free of hardware multipliers and use less number of hardware resources compared to the multiply-and-accumulate-based implementation.

An Efficient Distributed Arithmetic-Based Realization of the Decision Feedback Equalizer

A Distributed Arithmetic (DA) based scheme for the implementation of Sign-LMS adaptive filter is presented. DA is an efficient technique for the computation of the dot product of two vectors. This is done by storing the pre-computed partial-products in memories which are then shift-accumulated for the computation of the output. DA can be used for the realization of the finite impulse response (FIR) filters, however, for the realization of the adaptive filters, the partial-products have to be updated from time to time. This is achieved by using a memory which stores the partial-products of the set of recent input samples. The proposed scheme has a convergence performance similar to that of the multiply-and-accumulate (MAC) based implementation. Results show that the throughput of the DA based implementation is better than the MAC based implementation. Further, it is observed that the throughput is almost a constant with respect to the filter order which makes it more suitable for implementing large filters.

A distributed arithmetic based approach for the implementation of the Sign-LMS adaptive filter

This paper presents a distributed arithmetic (DA) based approach for the implementation of signedregressor LMS adaptive filter. DA, although is an efficient technique for the implementation of fixed coefficient filters, the adaptive filter implementation using DA is not a straight-forward task as the partialproducts of the filter weights have to be updated in every iteration. This is achieved by storing the partialproducts of the signum values of the input samples in a look-up-table (LUT). It has been shown that this LUT can be updated to accommodate the partial-products of newest set of samples in an efficient way using the circular- shifting of its address bits. Results indicate that the proposed filter can give better throughputs compared to multiply-and-accumulate (MAC) based implementation and can be effective when implementing large filters. With proper choice of system parameters, the proposed architecture for a 32- tap filter consumes around 87% less number of adder units while providing similar throughput performance compared to most recent existing DA based architecture.

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A Distributed Arithmetic Based Approach for the Realization of the Signed-Regressor LMS Adaptive Filter

In this paper, we propose a low complex architectural design for adaptive decision feedback equalizer (ADFE). For this we recast the ADFE equations using distributed arithmetic (DA), which enables the implementation of ADFE without multipliers. The design is based on the distributed arithmetic based formulation of it. It is further shown that high order filters, which are required to implement high speed ADFEs can be realized using only look-up-tables (LUTs) and shift-accumulate operations. A novel approach was proposed to replace feed forward and feedback filters of ADFE with a single DA unit. By proper initialization, it is also shown that a low complexity ADFE architecture can be obtained.

M. Surya Prakash

Papers

Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic

An Efficient Distributed Arithmetic-Based Realization of the Decision Feedback Equalizer

A distributed arithmetic based approach for the implementation of the Sign-LMS adaptive filter

A Distributed Arithmetic Based Approach for the Realization of the Signed-Regressor LMS Adaptive Filter

Low complexity hardware architectural design for adaptive decision feedback equalizer using distributed arithmetic