Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

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3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on insulator substrate or in a compound semiconductor substrate.

Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Dense arrays and charge storage devices

A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion.

Phase change memory cell and manufacturing method

Wafer Level 3-D ICs Process Technology

We report on 100-nm channel-length thin-film transistors (TFTs) that are fabricated using germanium-seeded lateral crystallization of amorphous silicon. Germanium seeding allows the fabrication of devices with control over grain boundary location. Its effectiveness improves with reduced device geometry, allowing "single-grain" device fabrication. In the first application of this technology to deep submicron devices, we report on 100-nm devices having excellent performance compared to conventional TFTs, which have randomly located grains. Devices have on-off ratio >10/sup 6/ and subthreshold slope of 107 mV/decade, attesting to the suitability of germanium-seeding for the fabrication of high-performance TFTs, suitable for use in vertically integrated three-dimensional (3-D) circuits.

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Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications

N-polar AlN epilayers were grown on the N-face of single-crystal bulk AlN substrates by plasma-assisted molecular beam epitaxy. A combination of in situ thermal deoxidation and Al-assisted thermal desorption at high temperature aided in removing native surface oxides and impurities from the N-polar surface of the substrate enabling successful homoepitaxy. Subsequent epitaxial growth of the AlN layer on the in situ cleaned substrates, grown in a sufficiently high Al droplet regime, exhibited smooth surface morphologies with clean and wide atomic steps. KOH etch studies confirmed the N-polarity of the homoepitaxial films. Secondary ion mass spectrometry profiles show Si and H impurity concentrations below the noise levels, whereas O and C impurity concentrations of [Formula: see text] and [Formula: see text] atoms/cm3 are observed, respectively. Although the structural defect densities are low, they interestingly appear as inversion domains of different dimensionalities.

https://aip.scitation.org/doi/pdf/10.1063/5.0100225

Molecular beam homoepitaxy of N-polar AlN on bulk AlN substrates

An aluminum nitride (AlN) quasi-vertical Schottky barrier diode (SBD) was fabricated on an AlN bulk substrate. An undoped AlN layer, a Si-doped Al0.9Ga0.1N current spreading layer and an AlN buffer layer were grown by plasma-enhanced molecular beam epitaxy. The epitaxial AlN layer was etched down to the n-Al0.9Ga0.1N layer to form an Ohmic contact. Ni/Au and V/Al/Ni/Au were deposited on the top AlN layer as Schottky contacts and on the exposed n-Al0.9Ga0.1N layer as Ohmic contacts, respectively. The Ohmic characteristics on the n-Al0.9Ga0.1N layer, capacitance–voltage (C–V) and current–voltage (I–V) characteristics of the AlN SBD were investigated.

AlN quasi-vertical Schottky barrier diode on AlN bulk substrate using Al0.9Ga0.1N current spreading layer

The polarization difference and band offset between Al(Ga)N and GaN induce two-dimensional (2D) free carriers in Al(Ga)N/GaN heterojunctions without any chemical doping. A high-density 2D electron gas (2DEG), analogous to the recently discovered 2D hole gas in a metal-polar structure, is predicted in a N-polar pseudomorphic GaN/Al(Ga)N heterostructure on unstrained AlN. We report the observation of such 2DEGs in N-polar undoped pseudomorphic GaN/AlGaN heterostructures on single-crystal AlN substrates by molecular beam epitaxy. With a high electron density of ∼4.3 [Formula: see text]/cm2 that maintains down to cryogenic temperatures and a room temperature electron mobility of ∼450 cm2/V s, a sheet resistance as low as ∼320 [Formula: see text] is achieved in a structure with an 8 nm GaN layer. These results indicate significant potential of AlN platform for future high-power RF electronics based on N-polar III-nitride high electron mobility transistors.

High-density polarization-induced 2D electron gases in N-polar pseudomorphic undoped GaN/Al0.85Ga0.15N heterostructures on single-crystal AlN substrates

Recent observation of high density polarization-induced two-dimensional electron gases in ultra-thin N-polar GaN layers grown on single-crystal AlN has enabled the development of N-polar high electron mobility transistors (HEMTs) on AlN. Such devices will take advantage of thermal and power handling capabilities of AlN, while simultaneously benefitting from the merits of N-polar structures, such as a strong back barrier. We report the experimental demonstration of N-polar GaN/AlGaN/AlN HEMTs on single-crystal AlN substrates, showing an on-current of 2.6 A/mm with a peak transconductance of 0.31 S/mm. Small-signal RF measurements revealed speeds exceeding ft/ fmax = 68/100 GHz. These results pave the way for developing RF electronics with excellent thermal management based on N-polar single-crystal AlN.

M. Toita

Papers

Low-leakage germanium-seeded laterally-crystallized single-grain 100-nm TFTs for vertical integration applications

Molecular beam homoepitaxy of N-polar AlN on bulk AlN substrates

AlN quasi-vertical Schottky barrier diode on AlN bulk substrate using Al0.9Ga0.1N current spreading layer

High-density polarization-induced 2D electron gases in N-polar pseudomorphic undoped GaN/Al0.85Ga0.15N heterostructures on single-crystal AlN substrates

N-polar GaN/AlGaN/AlN high electron mobility transistors on single-crystal bulk AlN substrates