M
M.Z. Straayer
Researcher at Massachusetts Institute of Technology
Publications - 11
Citations - 1374
M.Z. Straayer is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Noise shaping & Ring oscillator. The author has an hindex of 9, co-authored 10 publications receiving 1312 citations.
Papers
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Journal ArticleDOI
A 12-Bit, 10-MHz Bandwidth, Continuous-Time $\Sigma\Delta$ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: The use of VCO-based quantization within continuous-time (CT) SigmaDelta analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 mum CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth.
Journal ArticleDOI
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: An 11-bit, 50-MS/s time-to-digital converter (TDC) using a multipath gated ring oscillator with 6 ps of effective delay per stage demonstrates 1st-order noise shaping.
Proceedings Article
A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
M.Z. Straayer,Michael H. Perrott +1 more
TL;DR: The use of VCO-based quantization within continuous-time (CT) ΣΔ analog-to-digital converter (ADC) structures is explored, with a custom prototype in 0.13 μm CMOS showing measured performance of 86/72 dB SNR/SNDR with 10 MHz bandwidth.
Journal ArticleDOI
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance
TL;DR: In this article, the authors present a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve sub-picosecond jitter performance.
Proceedings Article
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance
TL;DR: In this article, the authors present a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve sub-picosecond jitter performance.