Object tracking based on active contour modeling is an image processing related technology that uses snapshots of the object under consideration to track it via robot in the real world. Nowadays, the word is moving towards the internet of things (IoTs) and having significant effect on our daily life. In this work, we have designed IoTs enable power efficient and thermal aware frame buffer to store the frames and uses that frame to detect changes in object position. In order to make IoTs enable design, we are embedding a 128-bit IPv6 address into frame buffer. In order to test the compatibility of this design with wireless network, we are operating this design with different operating frequency of WLAN channel. The operating frequency of WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, 802.11p and 802.11d are 900 MHz, 2.4, 3.6, 5, 5.9 and 60 GHz respectively. There is no change in signal power, clock power, IO power, when we scale down ambient temperature from 70 to 30 °C. There are 98---89 % saving in signal power, 2---85 % reduction in clock power, 90---99 % saving in IO power with WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, 802.11p in compare to power dissipation with 802.11ad. There is 71.11, 72.60, 73.96, 74.28, and 74.42 % reduction in leakage power with WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, and 802.11p, when we scale down ambient temperature from 70 to 30 °C. IoTs enable frame buffer design can be controlled from any part of this globe. Another design characteristic of this frame buffer is that it is 3-D frame buffer which gives us an added advantage over 2-D frame buffer that store image only in X, Y orientation. Capability to analyze third dimension helps us to track object more efficiently.

IoTs Enable Active Contour Modeling Based Energy Efficient and Thermal Aware Object Tracking on FPGA

Punjabi is ranked 1st in languages of Pakistan [5], 11th in Indian languages [6] and 3rd in Indian Subcontinent. In order to write Punjabi: Gurmukhi script is used in India and Shahmukhi in Pakistan. A lot of research is going on in Pakistan and India in the domain of natural language processing but, no research group is working especially for Punjabi to design Unicode reader. The Unicode range of characters for Gurmukhi script is 0x0A01-0x0A75. In this work, we are trying to fill this research gap in Punjabi natural language processing. This paper covers the hardware design and implementation of Punjabi Unicode Reader (PUR) for Gurmukhi scripts on Virtex-6 FPGA. This PUR design was tested with device operating frequency of 25 MHz, 125 MHz, 625 MHz, 1 GHz and 25 GHz. HSTL (High Speed Transceiver Logic) and I/O standard is used to make this design more energy efficient. Using HSTL_I_12, 38–50% I/O power was noticed and while using HSTL_II,the saving increases to 49–61%, with the device operating in range of 25MHz to 25GHz.This Unicode reader can count the number of vowel, consonants, and digit when used with counter.

http://ieeexplore.ieee.org/iel7/7012141/7029304/07029321.pdf

Simulation of HSTL IO standard based energy efficient Punjabi Unicode reader on FPGA

In this work, our main concern is thermal aware design on 28nm technology based Artix-7 FPGA. Thermal aware means, this design is able to operate in both extreme and normal temperature. LVCMOS (Low voltage Complementary Metal Oxide Semiconductor) is used as IO Standard. Using LVCMOS18, there is 93.03%, 66.58%, and 33.55% reduction in junction temperature, when we scale down ambient temperature from 75 ° C to 5 ° C, 25 ° C and 50 ° C respectively. Using LVCMOS25, there is 64.45%, 59.71% and 44.07% reduction in leakage power, when we scale down ambient temperature from 75 ° C to 5 °C, 25 °C and 50 °C respectively. In this paper, we have taken two different airflows. Linear Feet per Minute (LFM) is unit of airflow (distance traveled per unit of time). It is either 250 or 500 LFM for the Artix-7 FPGA. TJA is Theta Junction to Ambient (° C/W), Thermal power, TJC (Theta Junction to Case thermal resistance), TCS (Theta Case to hit Sink thermal resistance) and TSA (Theta Sink to Ambient thermal resistance) is also under consideration.

Thermal aware energy efficient comparator design using LVMOS IO standards on 28nm FPGA

In this work, we are we are going to search the most thermal and energy efficient IO Standards among the HSTL family and I2C family on 45 nm technology based FPGA. Here we are also doing thermal analysis for 273.15K-343.15K temperature, while during comparing the different IO Standards, we are taking the improvement level at 283.15K. In leakage power analysis, we are getting 9.09% improvement in HSTL with respect to others and in IO power analysis I2C shows 57.89% improvement with respect to others. In thermal analysis for maximum ambient temperature, we observe 1.79% improvement in HSTL_II as compared to others and in Junction Temperature analysis HSTL_I and I2C are 3.6% efficient than others. HSTL_I has minimum Theta Junction to Ambient Temperature value. In this work, we are using 45nm Spartan-6 FPGA. . We are taking airflow of 250LFM where LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

I2C and HSTL IO Standard Based Low Power Thermal Aware Adder Design on 45nm FPGA

Increasing the speed of computer is one of the important aspects of the Random Access Memory (RAM) and for better and fast processing it should be efficient. In this work, the main focus is to design energy efficient RAM and it also can be accessed through internet. A 128-bit IPv6 address is added to the RAM in order to control it via internet. Four different types of Low Voltage CMOS (LCVMOS) IO standards are used to make it low power under five different WLAN frequencies is taken. At WLAN frequency 2.4GHz, there is maximum power reduction of 85% is achieved when LVCMOS12 is taken in place of LVCMOS25. This design is implemented using Virtex-6 FPGA, Device xc6vlx75t and Package FF484

WLAN Specific IoT Enable Power Efficient RAM Design on 40nm FPGA

This paper proposes HSTL based energy efficient design of frame buffer for a digital image processor. Our aim is to make energy efficient frame buffer design and for that reason we are using different types of HSTL IO standards. This design is implemented on both Virtex-6 FPGA and Airtex-7 FPGA and compared the power dissipation. It is observed that at 1GHz operating frequency, there is maximum IO power reduction of 79.49% for HSTL_I IO standard with Airtex-7 FPGA as compared to Virtex-6 FPGA. For HSTL_II_18, at 1THz, we are getting minimum IO power reduction of 5.90% with Virtex-6 FPGA as compared to Airtex-7 FPGA. For Airtex-7 FPGA, XC7A100T device, −3 speed grades, and CSG2324 package is used and For Virtex-6 FPGA, XC6VLX75T, −1 speed grade and FF484 package is used.

Madhu M Limbu

Papers

Simulation of HSTL I/O standard based energy efficient frame buffer for digital image processor