Maire Mahony

TL;DR: This paper evaluates a custom ASIC-called a Tensor Processing Unit (TPU)-deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN) and compares it to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the samedatacenters.

TL;DR: The Tensor Processing Unit (TPU) as discussed by the authors is a custom ASIC deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN) using a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS).

TL;DR: In this paper, the authors describe the design and deployment of a new accelerator targeted at warehouse-scale video transcoding, and discuss key design trade-offs for balanced systems at data center scale and co-designing accelerators with large-scale distributed software systems.

TL;DR: In this paper, the authors describe a circuit that includes a device and a switch, which is coupled to the device to control power applied on the device, and the switch remains open when a supply voltage is applied to one of the two other terminals while powering-up the circuit.

TL;DR: In this paper, an apparatus and method for initializing electrical devices based on a voltage level is presented. But the voltage level may be modified to a particular setting based on the availability of power supply components, such as AC to DC rectifiers.