A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

https://iopscience.iop.org/article/10.7567/JJAP.56.04CD11/pdf

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

An innovative technology named FinFET (Fin Field Effect Transistor) has been developed to offer better transistor circuit design and to compensate the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices faces some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents etc. However, it is necessary for the memory to have less power dissipation, short access time and low leakage current. The traditional design of SRAM (Static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a Nano-scaled device named FinFET is introduced for designing SRAM since it has three dimensional design of the gate. FinFET has been used to improve the overall performance and has been chosen as a transistor of choice because it is not affected by SCEs. In this work, we have reviewed various FinFET based SRAM cells, performance metrics and the comparison over different technologies. 

A Review on SRAM Memory Design Using FinFET Technology

Overview of Different Technologies for Multiple-Valued Memory

MVL Random Access Memory

Digital systems are designed using binary radix which works on two-valued logic popularly known as low (0) and high (1). The logic operations are performed using underlying transistor switching actions. However, further reduction in minimum feature size of the transistors implementing binary-based digital systems is severely challenged by heat dissipation among other issues. To further improve the packing density, researchers are looking for higher radix number system over aggressive device scaling. Higher radix system is capable of reducing the number of wire interconnects. Ternary logic provides a good alternative to existing binary system logic in terms of reduced interconnects and higher operating speeds. Ternary logic devices are expected to offer a significant increase in information handling capability over binary logic systems. The present paper proposes a circuit for ternary to binary half adder using CMOS technology. The circuit for ternary decoder, ternary logic gates (TNOR, TAND, TOR), ternary inverters (STI, PTI, NTI), and T-buffer are also designed. The proposed design has been simulated using the CADENCE tool with 90 nm CMOS technology. The proposed ternary to binary adder circuit can be used as basic building block for different logic functions, and other important derived circuits like ternary memory, multiplier, and multiplexer. The proposed design of the ternary adder achieves lower power dissipation and improved power delay product. Furthermore, the results show the potential advantage of these half adders in complex arithmetic circuits for implementing the microprocessor and controllers. 

Designing of Ternary to Binary Half Adder Using CMOS

The Scaling of conventional CMOSs (Complementary Metal Oxide Semiconductors) has been facing problems such as short channel effect due to hot electron effect and leakage power. To solve the problems, FinFETs (Fin Field Effect Transistor) device structures are solution. Binary System occupies large area there for the circuit complexity is increasing on a VLSI chip and thus, degrading the performance of binary system. MVL (Multi valued logic) is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip, we have designed ternary Static Random Access Memory (SRAM) Cell using Shorted Gate FinFET (SG-FinFET). FinFET is double gate transistor architecture to extend scaling over planar device. Two gates have better control over the short channel effects. The paper presents a novel design of 6 Transistor ternary SRAM cell, with separate read and write lines. The proposed SRAM cell designed using Tanner tool version 13 and simulated with the help of W-Edit version 13.

Design of a ternary FinFET SRAM cell

The Scaling of conventional Complementary Metal Oxide Semiconductors (CMOSs) has been facing problems such as short channel effect due to hot electron effect and leakage power. Fin Field Effect Transistor (FinFET) is considered as solution to this issue. Binary system occupies large area there for the circuit complexity is increasing on a VLSI chip and thus degrading the performance of binary system. Multi valued logic MVL is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip I have designed FinFET based ternary basic gates (T-NOT, ST-NAND, ST-NOR, ST-AND and ST-OR). FinFET is classified in to two types based on gate structure: 1) Short Gate FinFET (SG-FinFET) and 2) Independent Gate FinFET (IG-FinFET). The proposed ternary logic gates are design using SG-FinFET. Simulation is performed with Tanner EDA tool. The proposed design has achieved good reduction in the circuit element count.

Makani Nailesh Kishor

Papers

Design of a ternary FinFET SRAM cell

A Novel FinFET Based Approach for the Realization of Ternary Gates