Design of a ternary FinFET SRAM cell

TLDR: The paper presents a novel design of 6 Transistor ternary SRAM cell, with separate read and write lines, using Shorted Gate FinFET (SG-FinFET), double gate transistor architecture to extend scaling over planar device.

Abstract: The Scaling of conventional CMOSs (Complementary Metal Oxide Semiconductors) has been facing problems such as short channel effect due to hot electron effect and leakage power. To solve the problems, FinFETs (Fin Field Effect Transistor) device structures are solution. Binary System occupies large area there for the circuit complexity is increasing on a VLSI chip and thus, degrading the performance of binary system. MVL (Multi valued logic) is considered as solution to this issue. In this paper, to minimize short channel effect and reduce circuit complexity on a VLSI chip, we have designed ternary Static Random Access Memory (SRAM) Cell using Shorted Gate FinFET (SG-FinFET). FinFET is double gate transistor architecture to extend scaling over planar device. Two gates have better control over the short channel effects. The paper presents a novel design of 6 Transistor ternary SRAM cell, with separate read and write lines. The proposed SRAM cell designed using Tanner tool version 13 and simulated with the help of W-Edit version 13.