Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

https://web.iitd.ac.in/~mamidala/HTMLobj-1518/dopingless_TFET_TED_Final.pdf

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

https://web.iitd.ac.in/~mamidala/HTMLobj-161/March04.pdf

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

I-CYP binding sites) was determinedafter 24 hours of isoproterenol treatment and ex-pressed as the percentage of receptor number as-sessed in nonstimulated cells. Where necessary,MG132 (20 mM) or lactacystin (20 mM) mixed inserum-free media was added to cells 1 hour beforestimulation.16. P. van Kerkhof, R. Govers, C. M. Alves dos Santos, G. J.Strous,

https://cml.harvard.edu/assets/science294_1313.pdf

Logic Gates and Computation from Assembled Nanowire Building Blocks

The Indian education system is one of the largest education systems in the world. Right from school to higher education, there are nearly 300 million students. India currently has about 41 million students in higher education, which will double in the coming years. In such an extensive system, diverse information or data are generated from multiple sources. Collecting and maintaining this data over time, keeping it up to date, and providing controlled access to it for policymaking, planning, and administration of education in the country is challenging.

Education Ecosystem Registry: How does it Change the Indian Education Landscape?

Although bipolar junction transistors (BJTs) are still used in the high‐frequency circuits such as in radio frequency circuits, the throne is captured by the metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) and they continue to drive the semiconductor industry even today. This chapter helps to develop a basic understanding of the conventional MOSFETs. It presents a subtle discussion of the various modes of operation of these devices. The chapter describes how basic circuits can be formed using MOSFETs. It discusses the implementation of circuits with the help of MOSFET as a switch. The chapter also describes the gate induced drain leakage (GIDL) in MOSFETs, which arises due to band‐to‐band tunnelling (BTBT), and the direct source to drain tunneling (DSDT). One of the approaches proposed to mitigate DSDT is to use a different crystal orientation of silicon for active device layer.

Introduction to Field‐Effect Transistors

Nanowire (NW) junctionless accumulation Mode (JAM) FETs were proposed to improve the ON-state current as compared to the conventional junctionless FETs. However, NWJAMFETs suffer from an enhanced detrimental lateral-band-to-band tunneling (L-BTBT) which restricts their scaling to sub-10 nm regime. Therefore, we investigate the scalability of NW JAMFETs using an intrinsic pocket in the extension regions. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket substantially reduces the L-BTBT induced OFF-state current by around 2 orders and 4 orders of magnitude for a gate length of 20 nm and 7 nm, respectively, leading to a significant ON-state to OFF-state current ratio (I ON /I OFF ) of 106 and 105, respectively and a small DIBL of 12mV/V and subthreshold swing (SS) of 62.2mV/dec for 20 nm gate length device. The NW JAMFET with intrinsic pocket (P i -NW JAMFET) exhibits superior short channel characteristics due to the reduced electrostatic source/channel-to-drain coupling and a diminished parasitic BJT action in the sub-10 nm regime extending the roadmap for the device scaling. The proposed P i -NW JAMFETs show superior performance even at a scaled contacted poly pitch (CPP) of 52 nm with I OFF ~28pA/um for a gate length of 7 nm. The excellent OFF-state characteristics of P i -NW JAMFET makes them a lucrative FET architecture for realizing sub-10 nm channel lengths for low power and low leakage applications.

Investigating the Scalability of Nanowire Junctionless Accumulation Mode FETs using an Intrinsic Pocket

Today technology is so advanced we can store thousands of books in a few gigabytes of memory. An enormous amount of information is also available on the Internet. But greater access to a massive amount of information is only worthwhile if we read the relevant material. That is why we must underline developing reading habits for our students. Students also need to comprehend and critically think about what they read from the books and other resources. Real learning ensues only then. When the students become good learners and remain life-long learners, that reflects the quality of education provided to them. Quality in Education is accomplished when students are motivated to accumulate adequate knowledge and skills and can proficiently utilize these tools to find pragmatic solutions to pressing challenges in their lives and careers.

Artificial Intelligence in Education: Are we ready?

Publishing research papers is integral to the academic activities of faculty members and students in higher educational institutes. Publishing in peer-reviewed journals is often a long process and involves revisions and re-writing. Peer-reviewed journals have a very rigorous reviewing process. Their editorial boards consist of distinguished scholars, and the work published in such journals is respected and cited by peers.

Mamidala Jagadesh Kumar

Papers

Education Ecosystem Registry: How does it Change the Indian Education Landscape?

Introduction to Field‐Effect Transistors

Investigating the Scalability of Nanowire Junctionless Accumulation Mode FETs using an Intrinsic Pocket

Artificial Intelligence in Education: Are we ready?

Beware of Predatory Journals