Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

https://web.iitd.ac.in/~mamidala/HTMLobj-1518/dopingless_TFET_TED_Final.pdf

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

https://web.iitd.ac.in/~mamidala/HTMLobj-161/March04.pdf

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

I-CYP binding sites) was determinedafter 24 hours of isoproterenol treatment and ex-pressed as the percentage of receptor number as-sessed in nonstimulated cells. Where necessary,MG132 (20 mM) or lactacystin (20 mM) mixed inserum-free media was added to cells 1 hour beforestimulation.16. P. van Kerkhof, R. Govers, C. M. Alves dos Santos, G. J.Strous,

https://cml.harvard.edu/assets/science294_1313.pdf

Logic Gates and Computation from Assembled Nanowire Building Blocks

In this letter, we present a study that highlights the importance of electrostatic effects on DNA sequence orientation, and the subsequent influence on the functioning principles of nanogap embedded dielectric-modulated field effect transistor (DMFET) biosensors. We find that the orientation of DNA molecules is responsible for governing the sensitivity and dominance of charge or dielectric constant effect in nanogap embedded FET devices. Using 2-D TCAD simulations, the study not only provides a correct explanation for the observed trend of threshold voltage shifts for DNA detection using n-channel DMFET, which has been loosely attributed to the dominance of the charge effect, but also gives insight into the reason of higher sensitivity of p-channel over n-channel DMFET biosensors.

Dielectric-Modulated Field Effect Transistors for DNA Detection: Impact of DNA Orientation

In this paper, we propose a double gate junctionless FET (DGJLFET) with an extended back gate (EBG) architecture for significantly improved performance in the sub-10-nm regime. Even for a channel length of 5 nm, we show using calibrated 2-D simulations that the EBG DGJLFET, when compared with the DGJLFET, exhibits: 1) an improved subthreshold swing; 2) a significantly low off-state leakage current; and 3) a considerably high $I_{\mathrm{\scriptscriptstyle ON}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ratio of $\sim 10^{8}$ . Furthermore, we demonstrate, for the first time, that the quantum confinement-induced bandgap widening diminishes the parasitic bipolar junction transistor (BJT) action and, therefore, facilitates the scaling of the conventional DGJLFETs to the sub-5-nm channel regime where the quantization effects are significant. Moreover, we also show, for the first time, that the DG junctionless accumulation mode FET suffers from an enhanced parasitic BJT action and, therefore, a significantly high off-state leakage current compared with the DGJLFET. In addition, we demonstrate that the loss of gate control for negative gate voltages in the DGJLFETs with larger silicon film doping ( $N_{D} \geq 2 \times 10^{19}$ cm $^{-3}$ ) is due to a shielding effect initiated by the band-to-band tunneling.

Symmetric Operation in an Extended Back Gate JLFET for Scaling to the 5-nm Regime Considering Quantum Confinement Effects

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.

https://web.iitd.ac.in/~mamidala/HTMLobj-617/TED_04_06a.pdf

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

In this brief, we propose a new stepped oxide hetero-material trench power MOSFET with three sections in the trench gate (an N+ poly gate sandwiched between two P+ poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving the following: 1) a good gate control on the channel charge and 2) a lesser gate-to-drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high-speed switching applications. In addition, the sandwiched gate with different work-function gate materials modifies the electric field profile in the channel, resulting in an improved breakdown voltage. By using 2-D simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance, and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench-gate MOSFET.

https://web.iitd.ac.in/~mamidala/HTMLobj-1095/saxena_june2009.pdf

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

The possibility of fast label-free detection of biomolecules using electronic devices has resulted in an increased focus on developing such biosensing devices and optimizing their structure for enhanced performance. One of the main factors that determine biosensor’s performance is its sensitivity. A high sensitivity in detecting biomolecules is achieved with FET-based biosensors by biasing the device in the subthreshold regime. Recent works have shown the possibility of significantly increased sensitivity in detecting biomolecules using emerging steep subthreshold slope FETs as label-free biosensors. A lower subthreshold swing, achievable with steep subthreshold slope devices, also results in a faster response time for the biosensor. The impact-ionization MOS (I-MOS) transistor can achieve very steep subthreshold slopes as it is turned ON abruptly due to the impact ionization phenomenon. In this paper, we propose an underlap I-MOS (UI-MOS) transistor sensor for the label-free detection of the charged biomolecules. The UI-MOS is a three-terminal device with an underlap in the middle of the gate electrode serving as the location for immobilization by biomolecules. The gate electrode of the UI-MOS offers the advantage of individual addressability of biosensors in a sensor array. The compatibility of the UI-MOS with the CMOS process enables monolithic integration with the measurement circuitry. Using the TCAD simulation, we demonstrate that a biosensor based on the UI-MOS is highly sensitive to the presence of charged biomolecules. The UI-MOS, when operating in the linear regime, also experiences a large threshold voltage ( $V_{T}$ ) shift due to the presence of biomolecules. The performance of UI-MOS is found to be less sensitive to gate-oxide thickness variations, and shows high sensitivity for a range of gate and underlap lengths. The very high sensitivity of the UI-MOS biosensor and its compatibility with the existing CMOS processes make it an exciting alternative to the conventional FET-based biosensors.

Mamidala Jagadesh Kumar

Papers

Dielectric-Modulated Field Effect Transistors for DNA Detection: Impact of DNA Orientation

Symmetric Operation in an Extended Back Gate JLFET for Scaling to the 5-nm Regime Considering Quantum Confinement Effects

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

Charge-Modulated Underlap I-MOS Transistor as a Label-Free Biosensor: A Simulation Study