Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

https://web.iitd.ac.in/~mamidala/HTMLobj-1518/dopingless_TFET_TED_Final.pdf

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

https://web.iitd.ac.in/~mamidala/HTMLobj-161/March04.pdf

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET

I-CYP binding sites) was determinedafter 24 hours of isoproterenol treatment and ex-pressed as the percentage of receptor number as-sessed in nonstimulated cells. Where necessary,MG132 (20 mM) or lactacystin (20 mM) mixed inserum-free media was added to cells 1 hour beforestimulation.16. P. van Kerkhof, R. Govers, C. M. Alves dos Santos, G. J.Strous,

https://cml.harvard.edu/assets/science294_1313.pdf

Logic Gates and Computation from Assembled Nanowire Building Blocks

A new analytical model for the surface potential and threshold voltage of a surrounding-gate MOSFET with dual-material gate is presented to investigate the short-channel effects. The model results accurately predict the threshold-voltage "roll off" for channel lengths even less than 90nm. The accuracy of the model results is verified using two-dimensional simulation.

https://web.iitd.ac.in/~mamidala/HTMLobj-616/TED_04_06b.pdf

New dual-material SG nanoscale MOSFET: analytical threshold-voltage model

In this paper, we investigate the nature of lateral band-to-band-tunneling (L-BTBT) component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET (NWJLFET) configurations for the first time. Although the NW junctionless accumulation mode (JAM) FET has a larger ON-state current compared with the NWJLFETs, we demonstrate that the L-BTBT GIDL is larger in the NWJAMFET compared with the NWJLFET. Furthermore, we explore for the first time the application of a dual-material gate (DMG) in the NWJAMFET to suppress the L-BTBT GIDL. Using calibrated 3-D simulations, we show that the OFF-state current in the DMG NWJAMFET is reduced significantly by six orders of magnitude leading to a considerable ON-state to OFF-state current ratio ( $I/I_{{\mathrm{\scriptscriptstyle OFF}}})$ of $\sim 10^{10}$ . Furthermore, the DMG NWJAMFET offers: 1) an enhanced ON-state current and 2) a significantly reduced OFF-state current compared with the NWJLFETs. Furthermore, we also demonstrate that the DMG NWJAMFET exhibits a higher transconductance than the single material gate NWJAMFET in the saturation region. In addition, we also show that there is a tradeoff between the off-state current and the intrinsic delay and the cut-off frequency in the DMG NWJAMFET. Therefore, we provide the design guidelines for appropriately choosing the work functions of the dual gates and the ratio of the length of the dual gates to the total gate length.

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

In this paper, we give a physical insight into the diameter-dependent dominant leakage mechanisms in the nanowire junctionless (NWJL) FETs. Using calibrated 3-D simulations, we show that the off-state current in the NWJLFETs with nanowire diameter less than 10 nm is governed by the drain-induced barrier lowering and the consequent source-to-channel barrier height and barrier thinning, which controls the lateral band-to-band tunneling (L-BTBT)-induced parasitic bipolar junction transistor (BJT) action. Furthermore, the quantum confinement-induced bandgap enhancement is shown to lower the probability of L-BTBT, and hence acts as the dominant mechanism in reducing the off-state current of the NWJLFETs with sub-7 nm diameter. In addition, the hole accumulation due to L-BTBT induces a shielding effect, which results in an inefficient volume depletion, leading to a large off-state current in NWJLFETs with nanowire diameters >15 nm. Furthermore, the impact of gate sidewall spacer on the L-BTBT-induced parasitic BJT in NWJLFETs has also been investigated.

Diameter Dependence of Leakage Current in Nanowire Junctionless Field Effect Transistors

A new analytical model for the surface potential and the threshold voltage of a silicon-on-insulator (SOI) MOSFET with electrically induced shallow source/drain (S/D) junctions is presented to investigate the short-channel effects (SCEs). Dividing the SOI MOSFETs silicon thin film into three zones, the surface potential is obtained by solving the two-dimensional Poissons equation. Our model includes the effects of the body doping concentration, the lengths of the side and main gates and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide, and also the silicon thin film. Our model results reaffirm that the application of induced S/D extensions to the SOI MOSFET will successfully control the SCEs for channel lengths even less than 50 nm. Two-dimensional simulation results are used to verify the validity of this model, and quite good agreements are obtained for various cases.

Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions

In this paper, we provide a simple and effective solution to realize efficient volume depletion and therefore, significantly reduce the OFF-state leakage current of a junctionless FET (JLFET) by replacing the SiO2 by HfO2 in the buried oxide (BOX). Using calibrated 2-D simulations, we show that the JLFET with a high-k BOX (HB JLFET) exhibits a considerably high ${\mathrm{ I}}_{\mathrm{ ON}} /{\mathrm{ I}}_{\mathrm{ OFF}} $ ratio of $\sim 10^{6}$ even for a channel length of 20 nm. Further, we demonstrate that the use of a high-k BOX leads to a reduction in both gate capacitance ${\mathrm{ C}}_{\mathrm{ g}} $ and gate-to-drain feedback (Miller) capacitance ${\mathrm{ C}}_{\mathrm{ gd}} $ .

Mamidala Jagadesh Kumar

Papers

New dual-material SG nanoscale MOSFET: analytical threshold-voltage model

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

Diameter Dependence of Leakage Current in Nanowire Junctionless Field Effect Transistors

Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions

Realizing Efficient Volume Depletion in SOI Junctionless FETs