Manil Dev Gomony

TL;DR: This paper introduces the composability and predictability concepts, why they help, and how they are implemented in the different resources of the CompSOC architecture, and defines a design flow that allows real-time cyclo-static dataflow applications to be automatically mapped, verified, and executed.

TL;DR: A real-time multi-channel memory controller architecture with a new programmable Multi-Channel Interleaver unit and a novel method for logical-to-physical address translation that enables inter-leaving memory requests across multiple memory channels at different granularities are contributed.

TL;DR: This paper designs CA-DFA, an algorithm that, using only information available at layer two, adapts the amount of 802.11n aggregation used by a Wi-Fi station according to the level of congestion in the network, and demonstrates the benefits of this algorithm in terms of QoS, energy efficiency and network capacity with respect to state of the art alternatives.

TL;DR: The performance of GAMT is compared with centralized implementations and it is shown that it can run up to four times faster and have over 51 and 37 percent reduction in area and power consumption, respectively, for a given bandwidth.

TL;DR: This paper analyzes the worst-case bandwidth, average-case execution time, and power consumption of mobile DRAMs across three generations: L PDDR, LPDDR2 and Wide-IO-based 3D-stacked DRAM, and proposes a methodology for selecting memory configurations in real-time mobile systems.