While programmable NICs allow for better scalability to handle growing network workloads, providing an expressive yet simple abstraction to program stateful network functions in hardware remains a research challenge. We address the problem with FlowBlaze, an open abstraction for building stateful packet processing functions in hardware. The abstraction is based on Extended Finite State Machines and introduces the explicit definition of flow state, allowing FlowBlaze to leverage flow-level parallelism. FlowBlaze is expressive, supporting a wide range of complex network functions, and easy to use, hiding low-level hardware implementation issues from the programmer. Our implementation of FlowBlaze on a NetFPGA SmartNIC achieves very low latency (in the order of a few microseconds), consumes relatively little power, can hold per-flow state for hundreds of thousands of flows, and yields speeds of 40 Gb/s, allowing for even higher speeds on newer FPGA models. Both hardware and software implementations of FlowBlaze are publicly available.

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FlowBlaze: Stateful Packet Processing in Hardware

Hardware implementation of Floating Point Units (FPUs) has been a key area of research due to their massive area and energy footprints. Recently, a proposal was made to replace IEEE 754-2008 technical standard compliant FPUs with Posit Arithmetic Units (PAUs) due to the greater accuracy, speed, and simpler hardware design. In this paper, we present the architecture of a parameterized PAU generator that can generate PAU adders and PAU multipliers of any bit-width pre-synthesis. We synthesize generated arithmetic units using the parameterized PAU generator for 8-bit, 16-bit, and 32-bit adders and multipliers and compare them with IEEE 754-2008 compliant adders and multipliers. Both, synthesis for Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) are performed. In our comparison of m-bit PAU units with n-bit IEEE 754-2008 compliant units, it is observed that the area and energy of a PAU adder and multiplier are comparable to their IEEE 754-2008 compliant counterparts where m=n. We argue that an n-bit IEEE 754-2008 adder and multiplier can be safely replaced with an m-bit PAU adder and multiplier where m<n, due to superior numerical accuracy of the PAU; we also compare m-bit PAU adders and multipliers with n-bit IEEE 754-2008 compliant adders and multipliers. As an application example, we examine performance in the domain of signal processing with and without PAU adders and multipliers, and show the advantage of our approach.

Parameterized Posit Arithmetic Hardware Generator

Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing designs support only a small TCAM size even with large FPGA devices. They also suffer from significant throughput degradation in implementing a large TCAM, mainly caused by deep priority encoding. This paper presents a scalable random access memory (RAM)-based TCAM architecture aiming for efficient implementation on state-of-the-art FPGAs. We give a formal study on RAM-based TCAM to unveil the ideas and the algorithms behind it. To conquer the timing challenge, we propose a modular architecture consisting of arrays of small-size RAM-based TCAM units. After decoupling the update logic from each unit, the modular architecture allows us to share each update engine among multiple units. This leads to resource saving. The capability of explicit range matching is also offered to avoid range-to-ternary conversion for search functions that require range matching. Implementation on a Xilinx Virtex 7 FPGA shows that our design can support a large TCAM of up to 2.4 Mbits while sustaining high throughput of 150 million packets per second. The resource usage scales linearly with the TCAM size. The architecture is configurable, allowing various performance trade-offs to be exploited. To the best of our knowledge, this is the first FPGA design that implements a TCAM larger than 1 Mbits.

Scalable ternary content addressable memory implementation using FPGAs

Recent advances in ultra-high-throughput microscopy have enabled a new generation of cell classification methodologies using image-based cell phenotypes alone. In contrast to current single-cell analysis techniques that rely solely on slow and costly genetic/epigenetic analysis, these image-based analyses allow morphological profiling and screening of thousands or even millions of single cells at a fraction of the cost, and have been proven to demonstrate the statistical significance required for understanding the role of cell heterogeneity in diverse biological applications, ranging from cancer screening to drug candidate identification/validation processes. This paper examines the efficacies and opportunities presented by machine learning algorithms in processing large scale datasets with millions of label-free cell images. An automatic single-cell classification framework using convolutional neural network (CNN) has been developed. A comparative analysis of its efficiency in classifying large datasets against conventional k-nearest neighbors (kNN) and support vector machine (SVM) based methods are also presented. Experiments have shown that our proposed framework can efficiently identify multiple types cells with over $99\%$ accuracy based on the phenotypic label-free bright-field images; and CNN-based models perform well and relatively stable against data volume compared with kNN and SVM.

Large-Scale Multi-Class Image-Based Cell Classification With Deep Learning

This paper proposes open-source hardware P osit A rithmetic Co re Gen erator (PACoGen) for the recently developed universal number posit number system, along with a set of pipelined architectures. The posit number system composed of a run-time varying exponent component, which is defined by a composition of varying length “regime-bit” and “exponent-bit” (with a maximum size of ES bits, the exponent size). This in effect also makes the fraction part to vary at run-time in size and position. These run-time variations inherit an interesting hardware design challenge for posit arithmetic architectures. The posit number system, being at an infant stage of its development, possess very limited hardware solutions for its arithmetic architectures. In this view, this paper targets the algorithmic development and generic HDL generators (PACoGen) for basic posit arithmetic. The proposed open source PACoGen currently includes the adder/subtractor, multiplier, and division arithmetic. The PACoGen can provide the Verilog HDL code respective posit arithmetic for any given posit word width (N) and exponent size (ES), as defined under the posit number system. Further, pipelined architectures of 32-bit posit with 6-bit exponent size are also proposed and discussed for addition/subtraction, multiplication, and division arithmetic. The proposed posit arithmetic architectures are demonstrated on the Virtex-7 (xc7vx330t-3ffg1157) FPGA device as well as Nangate 15 nm ASIC platform. The PACoGen would open a gateway for further posit arithmetic hardware exploration and evaluation.

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PACoGen: A Hardware Posit Arithmetic Core Generator

Ternary content addressable memories (TCAMs) perform high-speed lookup operation but when compared with static random access memories (SRAMs), TCAMs have certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and are very expensive. Thus, can we use the benefits of SRAM by configuring it (with additional logic) to enable it to behave like TCAM? This brief proposes a novel memory architecture, named Z-TCAM, which emulates the TCAM functionality with SRAM. Z-TCAM logically partitions the classical TCAM table along columns and rows into hybrid TCAM subtables, which are then processed to map on their corresponding memory blocks. Two example designs for Z-TCAM of sizes 512 $\,\times\,$ 36 and 64 $\,\times\,$ 32 have been implemented on Xilinx Virtex-7 field-programmable gate array. The design of 64 $\,\times\,$ 32 Z-TCAM has also been implemented using OSUcells library for 0.18 $\mu{\rm m}$ technology, which confirms the physical and technical feasibility of Z-TCAM. Search latency for each design is three clock cycles. The detailed implementation results and power measurements for each design have been reported thoroughly.

Z-TCAM: An SRAM-based Architecture for TCAM

Decomposition of a matrix into lower and upper triangular matrices (LU decomposition) is a vital part of many scientific and engineering applications, and the block LU decomposition algorithm is an approach well suited to parallel hardware implementation This paper presents an approach to speed up implementation of the block LU decomposition algorithm using FPGA hardware Unlike most previous approaches reported in the literature, the approach does not assume the matrix can be stored entirely on chip The memory accesses are studied for various FPGA configurations, and a schedule of operations for scaling well is shown The design has been synthesized for FPGA targets and can be easily retargeted The design outperforms previous hardware implementations, as well as tuned software implementations including the ATLAS and MKL libraries on workstations

FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture

Posit number system format includes a run-time varying exponent component, defined by a combination of regime-bit (with run-time varying length) and exponent-bit (with size of up to ES bits, the exponent size). This also leads to a run-time variation in its mantissa field size and position. This run-time variation in posit format poses a hardware design challenge. Being a recent development, posit lacks for its adequate hardware arithmetic architectures. Thus, this paper is aimed towards the posit arithmetic algorithmic development and their generic hardware generator. It is focused on basic posit arithmetic (floating-point to posit conversion, posit to floating point conversion, addition/subtraction and multiplication). These are also demonstrated on a FPGA platform. Target is to develop an open-source solution for generating basic posit arithmetic architectures with parameterized choices. This contribution would enable further exploration and evaluation of posit system.

Universal number posit arithmetic generator on FPGA

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of $$512\times 36$$ 512 × 36 of E-TCAM has been successfully implemented on Xilinx Virtex- $$5$$ 5 , Virtex- $$6$$ 6 , and Virtex- $$7$$ 7 field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains $$33.33$$ 33.33 % reduction in block-RAMs, $$71.07$$ 71.07 % in slice registers, $$77.16$$ 77.16 % in lookup tables, $$53.54$$ 53.54 % in energy/bit/search, and offers $$63.03$$ 63.03 % improvement in speed, compared with the best available SRAM-based TCAM designs.

Manish Kumar Jaiswal

Papers

Z-TCAM: An SRAM-based Architecture for TCAM

PACoGen: A Hardware Posit Arithmetic Core Generator

FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture

Universal number posit arithmetic generator on FPGA

E-TCAM: An Efficient SRAM-Based Architecture for TCAM