FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deep-submicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25-/spl mu/m CMOS appears to be the threshold for robust, low-NF RF front ends with current consumption competitive with today's BJT implementations.

The impact of scaling down to deep submicron on CMOS RF circuits

A digitally modulated power amplifier (DPA) in 1.2 V 0.13 mum SOI CMOS is presented, to be used as a building block in multi-standard, multi-band polar transmitters. It performs direct amplitude modulation of an input RF carrier by digitally controlling an array of 127 unary-weighted and three binary-weighted elementary gain cells. The DPA is based on a novel two-stage topology, which allows seamless operation from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a 25.2 dBm maximum envelope power. Adaptive digital predistortion is exploited for DPA linearization. The circuit is thus able to reconstruct 21.7 dBm WCDMA/EDGE signals at 1.9 GHz with 38% efficiency and a higher than 10 dB margin on all spectral specifications. As a result of the digital modulation technique, a higher than 20.1 % efficiency is guaranteed for WCDMA signals with a peak-to-average power ratio as high as 10.8 dB. Furthermore, a 15.3 dBm, 5 MHz WiMAX OFDM signal is successfully reconstructed with a 22% efficiency and 1.53% rms EVM. A high 10-bit nominal resolution enables a wide-range TX power control strategy to be implemented, which greatly minimizes the quiescent consumption down to 10 mW. A 16.4% CDMA average efficiency is thus obtained across a > 70 dB power control range, while complying with all the spectral specifications.

A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control

A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < ?-60 dBc beyond 1 GHz while driving a 50 ? load with an output swing of 2.5 Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9n GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with ?always-ON? biasing.

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A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$ 60 dBc Beyond 1 GHz in 65 nm CMOS

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm2.

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10 bit 1 GS/s current-steering CMOS D/A converter is presented. The measured INL is better than +/-0.2 LSB. The 1 GS/s conversion rate has been obtained by a fully custom designed thermometer decoder. The dynamic limitations have been solved, resulting in more than 61 dB measured SFDR in the interval from DC to Nyquist at all conversion rates up to 1 GS/s. At this conversion rate, the power consumption equals 110 mW. The chip has been processed in a standard 0.35 /spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

Since several years research has been carried out on the design of RF circuits in CMOS technologies. Since then, the usability of CMOS for RF design has been demonstrated by several research groups. However, there are still some fundamental problems and limitations which may not be overlooked. The purpose of this work is to present some of those ‘untold pitfalls’ in the design of RF CMOS circuits for fully integrated transceivers for telecommunication applications.

RF CMOS Design, Some Untold Pitfalls

Since several years the research in the possibilities of CMOS technologies for RF applications is growning enormously. The trend towards deep sub-micron technologies allows the operation frequency of CMOS circuits above 1GHz, which opens the way to integrated CMOS RF circuits. Several research groups have developed high performance down-converters, low phase noise voltage controlled oscillators and dual modulus prescalers in standard CMOS technologies. The research has already demonstrated fully integrated receivers and VCO circuits with no external components, nor tuning or trimming. Further research on low noise amplifiers, up-converters, synthesizers and power amplifiers will hopefully result in CMOS RF circuits for fully integrated transceivers for telecommunication applications.

Marc Borremans

Papers

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

RF CMOS Design, Some Untold Pitfalls

RF Integrated Circuits in Standard CMOS Technologies

A 2V CMOS Cellular Transeiver Front-End