Digital arithmetic plays an important role in the design of general-purpose digital processors and of embedded systems for signal processing, graphics, and communications. In spite of a mature body of knowledge in digital arithmetic, each new generation of processors or digital systems creates new arithmetic design problems. Designers, researchers, and graduate students will find solid solutions to these problems in this comprehensive, state-of-the-art exposition of digital arithmetic. Ercegovac and Lang, two of the field's leading experts, deliver a unified treatment of digital arithmetic, tying underlying theory to design practice in a technology-independent manner. They consistently use an algorithmic approach in defining arithmetic operations, illustrate concepts with examples of designs at the logic level, and discuss cost/performance characteristics throughout. Students and practicing designers alike will find Digital Arithmetic a definitive reference and a consistent teaching tool for developing a deep understanding of the "arithmetic style" of algorithms and designs. Guides readers to develop sound solutions, avoid known mistakes, and repeat successful design decisions. Presents comprehensive coveragefrom fundamental theories to current research trends. Written in a clear and engaging style by two masters of the field. Concludes each chapter with in-depth discussions of the key literature. Includes a full set of over 250 exercises, an on-line appendix with solutions to one-third of the exercises and 600 lecture slides

Digital arithmetic

Dynamic memory allocation has been a fundamental part of most computer systems since roughly 1960, and memory allocation is widely considered to be either a solved problem or an insoluble one. In this survey, we describe a variety of memory allocator designs and point out issues relevant to their design and evaluation. We then chronologically survey most of the literature on allocators between 1961 and 1995. (Scores of papers are discussed, in varying detail, and over 150 references are given.)

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Dynamic Storage Allocation: A Survey and Critical Review

Quiescent power supply current (I

 DDQ
 ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of I

 DDQ
 testing. Next, the use of I

 DDQ
 testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.

I DDQ testing: A review

Beyond energy, the growing number of defects in physical substrates is becoming another major constraint that affects the design of computing devices and systems. As the underlying semiconductor technologies are getting less and less reliable, the probability that some components of computing devices fail also increases, preventing designers from realizing the full potential benefits of on-chip exascale integration derived from near atomic scale feature dimensions. As the quest for performance confronts permanent and transient faults, device variation, and thermal issues, major breakthroughs in computing efficiency are expected to benefit from unconventional and new models of computation, such as brain-inspired computing. The challenge is then to find not only high-performance and energy-efficient, but also fault-tolerant computing solutions. Neural computing principles remain elusive, yet as source of a promising fault-tolerant computing paradigm. In the quest to fault tolerance can be translated into scalable and reliable computing systems, hardware design itself and/or to use circuits even with faults has further motivated research on neural networks, which are potentially capable of absorbing some degrees of vulnerability based on their natural properties. This paper presents a survey on fault tolerance in neural networks manly focusing on well-established passive techniques to exploit and improve, by design, such potential but limited intrinsic property in neural models, particularly for feedforward neural networks. First, fundamental concepts and background on fault tolerance are introduced. Then, we review fault types, models, and measures used to evaluate performance and provide a taxonomy of the main techniques to enhance the intrinsic properties of some neural models, based on the principles and mechanisms that they exploit to achieve fault tolerance passively. For completeness, we briefly review some representative works on active fault tolerance in neural networks. We present some key challenges that remain to be overcome and conclude with an outlook for this field.

Fault and Error Tolerance in Neural Networks: A Review

This paper presents a high-speed method for function approximation that employs symmetric bipartite tables. This method performs two parallel table lookups to obtain a carry-save (borrow-save) function approximation, which is either converted to a two's complement number or is Booth encoded. Compared to previous methods for bipartite table approximations, this method uses less memory by taking advantage of symmetry and leading zeros in one of the two tables. It also has a closed-form solution for the table entries, provides tight bounds on the maximum absolute error, and can be applied to a wide range of functions. A variation of this method provides accurate initial approximations that are useful in multiplicative divide and square root algorithms.

Approximating elementary functions with symmetric bipartite tables

The paper reviews the algorithms for the computation of square roots for binary machines. After an initial classification, the algorithms are analysed in detail by considering their specific peculiarities and properties. Finally, some comments are made regarding their ideal and effective implementation in hardware, software or microcode

Survey of Square Rooting Algorithms

The review paper deals with problems concerning fault modelling for LSI/VLSI devices. Both random and regular logic are considered, and different fault classes are discussed for each, including stuck-at, bridging, functional and time-dependent faults. Specific fault models are then considered for microprocessors, RAMs and PLAs

A review of fault models for lsi/vlsi devices

PART is a system for PLA testing and design verification, intended to be properly interfaced with other existing tools to generate a comprehensive design environment To this purpose, it provides several facilities, among which the capability of generating a fault population on the basis of layout information PART aims at producing a very compact test set for all detectable crosspoint defects, using limited amounts of run time and storage This is achieved by means of an efficient partitioning algorithm together with powerful heuristics Test minimality is ensured by a simple procedure In the present paper these are discussed, experimental results are given and a comparison with competing strategies is made

PART: Programmable Array Testing Based on a Partitioning Algorithm

Our university has offered a massive educational video service since 2010, as part of a blended learning model that allows students to balance active participation in the classroom with remote access to video-recorded lectures. In these years, we have collected a huge amount of very detailed data about the students' access to the service. Together with additional information that characterize a university system (e.g. students' performance or course population), these data represent a precious ground set to assess the educational model. The paper describes an experimental set to profile the use of the educational video service, whose results will contribute to improve the model. Specifically the paper analyzes the students' service use relatively to different transversal course characteristics, such as level, main topic, population, success rate. As a result, it outlines the profile of the “ideal” courses for which students highly appreciate the service. This information will help educational designers to select the future courses to be included in the service, but it will also give directions on the sectors where improvements are necessary. Finally, the paper experimentally demonstrates a positive impact of the educational video service on students' performance, and specifically on the exam success rate.

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Educational video services in universities: A systematic effectiveness analysis

This work discusses the main challenges and requirements of technical and legal authentication interoperability in e- services involving organizations from different countries. We present the Stork cross-border authentication framework that satisfies these requirements by establishing interoperability between existing European national eID infrastructures in a federated manner. As a sample application, we present the pilot for Student Mobility that has been developed to evaluate and demonstrate the functionality of the Stork authentication framework.

Marco Mezzalama

Papers

Survey of Square Rooting Algorithms

A review of fault models for lsi/vlsi devices

PART: Programmable Array Testing Based on a Partitioning Algorithm

Educational video services in universities: A systematic effectiveness analysis

Federating e-identities across Europe, or how to build cross-border e-services