Paolo Prinetto

TL;DR: In this paper, a comprehensive guide to fault injection techniques used to evaluate the dependability of a digital system is presented, along with a critical analysis of different fault injection tools and techniques.

TL;DR: A prototype system named GATTO is used to assess the effectiveness of the approach in terms of result quality and CPU time requirements and the results are the best ones reported in the literature for most of the largest standard benchmark circuits.

TL;DR: Different approaches to hardware verification are first examined, and formal verification and automated synthesis are compared to show how they cooperate in producing zero-defect designs.

TL;DR: The authors present a novel ATPG (automatic test pattern generation) algorithm, based on PODEM, that makes diagnostic test patterns generation feasible for medium-sized combinational circuits described at the gate level with the single-stuck-at-fault assumption.

TL;DR: An approach based on Genetic Algorithms suitable for even the largest benchmark circuits, together with a prototype system named GATTO is described and its effectiveness (in terms of result quality and CPU time requirements) for circuits previously unmanageable is illustrated.