Showing papers by "Marek Perkowski published in 1992"

A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping

Abstract: An approach to the decomposition of incompletely specified Boolean functions is introduced, and its application to lookup-table-based field programmable gate array (FPGA) mapping is described. Three methods are developed: fast graph coloring to perform a quasi-optimum 'don't care' assignment; variable partitioning to quickly find the 'best' partitions; and local transformation to transform a nondecomposable function into several decomposable ones. The methods perform global optimization of the input function. A short description of a FPGA mapping program (TRADE) and an evaluation of its results are provided. >

Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks

Abstract: The authors introduce fast exact and quasi-minimal algorithms for minimal fixed polarity AND/XOR canonical representation of Boolean functions. The method uses features of arrays of disjoint cubes representations of functions to identify the minimal networks. These features can drastically reduce the search space and provide high quality heuristics for quasi-minimal representations. Experimental results show that these special AND/XOR networks, on the average, have a similar number of terms to Boolean AND/OR networks while there were functions for which AND/XOR circuits were much smaller. The circuits generated are much more testable. >

Effective computer methods for the calculation of Rademacher-Walsh spectrum for completely and incompletely specified Boolean functions

Abstract: A theory has been developed to calculate the Rademacher-Walsh transform from a cube array specification of incompletely specified Boolean functions. The importance of representing Boolean functions as arrays of disjoint ON- and DC-cubes has been pointed out, and an efficient new algorithm to generate disjoint cubes from nondisjoint ones has been designed. The transform algorithm makes use of the properties of an array of disjoint cubes and allows the determination of the spectral coefficients in an independent way. The programs for both algorithms use advantages of C language to speed up the execution. The comparison of different versions of the algorithm has been carried out. The algorithm and its implementation provide the fastest and most comprehensive program (having many options) known to the authors for the calculation of the Rademacher-Walsh transform. It successfully overcomes all drawbacks in the calculation of the transform from the design automation system based on spectral method-the SPECSYS system from Drexel University, which uses fast Walsh transform. >

The generalized orthonormal expansion of functions with multiple-valued inputs and some of its applications

Abstract: The fundamental concept of generalized orthonormal expansion, which generalizes the ring forms of the Shannon expansion to logic with multivalued (MV) inputs and standard trivial functions of an arbitrary number of variables, is introduced. Some applications of the generalized orthonormal expansion are presented, including several generalizations of canonical forms both known from the literature and new. These include a family of canonical tree circuits, which are considered for binary and multivalued input cases. They can be multilevel or flattened to two-level AND-EXOR circuits. >

Fast minimization of mixed-polarity AND/XOR canonical networks

Abstract: A quasi-minimal algorithm for canonical restricted mixed polarity (CRMP) AND/XOR forms is presented. These forms, which include the consistent and inconsistent generalized Reed-Muller (GRM) forms, are both very easily testable and, on average, have smaller numbers of terms than sum-of-product (SOP) expressions. The set of test vectors for detecting stuck-at and bridging faults of a function realized in CRMP forms, like that of consistent (GRM) forms, is independent of the function. This test can be of order (n+4)r, where n is the number of variables in the function and r is the number of component consistent GRMs in the CRMP. The experimental results confirm the compactness of CRMPs as compared to SOP expressions. >

Minimization of Permuted Reed-Muller Trees for Cellular Logic

Abstract: The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, introduced by it new universal logic cell calls also for new logic synthesis methods based on regularity of connections. In this paper we present two programs, exact and approximate, for the minimization of Permuted Reed-Muller Trees that are obtained by repetitive application of Davio expansions (Shannon expansions for EXOR gates) in all possible orders of variables in subtrees. Such trees are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. It is shown on several standard benchmarks that the heuristic algorithm gives good quality results in much less time than the exact algorithm.

Minimization of permuted Reed-Muller Trees for cellular logic programmable Gate arrays

Abstract: The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, introduced by it new universal logic cell calls also for new logic synthesis methods based on regularity of connections. In this paper we present two programs, exact and approximate, for the minimization of Permuted Reed-Muller Trees that are obtained by repetitive application of Davio expansions (Shannon expansions for EXOR gates) in all possible orders of variables in subtrees. Such trees are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. It is shown on several standard benchmarks that the heuristic algorithm gives good quality results in much less time than the exact algorithm.

Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions

Abstract: A theory has been developed to calculate the Rademacher-Walsh transform from a reduced representation (disjoint cubes) of incompletely specified Boolean functions. The transform algorithm makes use of the properties of an array of disjoint cubes and allows the determination of the spectral coefficients in an independent way. The program for the algorithms uses advantages of C language to speed up the execution. The comparison of different versions of the algorithm has been carried out. The algorithm successfully overcomes all drawbacks in the calculation of the transform from the design automation system based on spectral methods. >

Canonical restricted mixed-polarity exclusive sums of products

Abstract: The concept of canonical restricted mixed polarity (CRMP) exclusive sum of products (ESOP) forms is introduced. It includes the inconsistent canonical Reed-Muller and generalized Reed-Muller forms as special cases. The set of CRMP forms is included in the set of ESOP expressions. An attempt to characterize minimal CRMP forms for completely specified Boolean functions is presented, as well as an attempt to gain insight into the complexity of computation needed to find such a form. Some fundamental properties unique to CRMPs are proved. It is also proved that the upper bound on the number of terms in the CRMP form is smaller than that in the conventional normal forms and is equal to that of the ESOPs. A theorem providing a lower bound on the number of CRMP terms is also given. These results prove the validity of the CRMP concept. An efficient generic heuristic algorithm to find the CRMP form is presented. >

Generation of adding and arithmetic multi-polarity transforms for incompletely specified boolean functions

Abstract: A new computer algorithm that generates adding and arithmetic multi-polarity transforms of completely and incompletely specified boolean functions is shown. The developed algorithm generates each spectral coefficient directly from the minterm representation of a function without performing a matrix multiplication. Thus, it is possible to calculate only partial spectra.

Fixed-Polarity AND/XOR Canonical Networks

Abstract: The high testability of AND/XOR networks and new technologies that make their use more possible call for new minimization and synthesis tools. This paper introduces the fast Exact and Quasi-minimal algorithms for minim al$xed polarity AND/XOR canonical representation of Boolean functions. The method uses features of array of disjoint cubes representation of functions to identify the minimal networks. These features can drastically reduce the search space and provide high quality heuristics for quasi-minimal representations. Experimental results show that these

A universal logic machine

Abstract: After a brief review of the history of logic machines, a description is given of the Cube Calculus Machine (CCM2). This machine is based on an architecture in which the data path has been designed to execute operations to cube calculus, an algebraic model popularly used to process and minimize Boolean functions. CCM2 realizes efficiently all cube calculus operations such as sharp and consensus. The positional cube representation used by CCM2 can also represent multivalued-input, binary-output cube calculus (MVCC) operands. CCM2 can also work with generalized MVCC, which was developed as an extension of MVCC. This extension allows the machine to operate on set logic, associative tuples, several multivalued input multivalued output logics, multioutput relations, and symbolic relations. >

Hierarchical Hough transform based on pyramidal architecture

Abstract: A hierarchical Hough transform (HT) based on pyramidal architecture is described, being a main component of the low-to-medium spatial vision subsystem for a mobile robot. The sequence of processing in the system originally conceived to be essential to the extraction of line features in indoor scenes consisted of: histogram equalization, smoothing with the use of a medial filter, edge detection using the Sobel edge detectors, binarization to extract the edges detected, labeling, rebinarization and thinning to refine the edges to thin lines, and line extraction using a hierarchical approach to the HT method. The task was to establish the importance of each step for the success of the hierarchical HT. It was implemented on a 386-based personal computer with 640 K memory and proved to give results of high quality as compared with the standard HT implementation. >

An exact algorithm for the technology fitting problem in the application specific state machine device

Abstract: The fitting problem for a new application-specific state machine device, CY7C361, from Cypress Semiconductor is formulated, and a solution is proposed. This fitting problem consists of mapping the netlist obtained from high-level synthesis into the chip's physical resources. In general, the mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints. The formulation is quite general for a class of electronically programmable logic device (EPLD) fitting problems. An exact, constraint-based, tree searching algorithm with several kinds of backtracking was implemented. >

The Cube Calculus Machine: a ring of asynchronous automata to process multiple-valued Boolean functions

Abstract: The authors propose a Cube Calculus Machine (CCM-1), a novel architecture in which the data path has been designed to execute operations of cube calculus, an algebraical model popularly used to process and minimize Boolean functions. The machine uses a 'positional cube representation', which can also represent the multiple-valued input algebra that finds many applications in logic synthesis. Another aspect of this architecture is the implementation of the processing unit as an iterative network of asynchronous finite state machines (FSMs). This is a new concept in computer architecture that can find applications wider than the CCM alone. CCM-1 realizes basic microinstructions that support the microcode implementation of all useful cube calculus operations including sharp, consensus, supercube, and crosslink. >

Object-oriented design of an expandable hardware description language analyzer for a high-level synthesis system

Abstract: The paper presents a new approach to high-level synthesis system design in which object-oriented programming techniques are used to construct an expansible hardware description language (HDL) analyzer. There are several major advantages of this new methodology over the traditional top-down approaches. The object-oriented data model for high-level synthesis systems is shown to be a better way to model the high-level synthesis design entities. A formal object oriented programming(OOP) model of high-level synthesis and systematic ways of expanding the system are also described. This design style influences the construction of the entire high-level synthesis system. The system has been successfully implemented in C++ and has proven to be reliable, expansible, and sufficiently fast. >

Automated synthesis of microprogrammed control units in DIADES

Abstract: Presents the automatic synthesis of microprogrammed control units in the DIADES design automation system. The optimization of the microcode is incorporated into a comprehensive process of data path scheduling and allocation and of control unit design. A new microprogrammed controller model that is suitable for design automation and formal description is described. This new model permits design and optimization of controllers ranging from a very basic microcontroller to a very complex one. The micro-sequencer architecture is retargetable. A symbolic intermediate microcode (SIMC) is generated as a high-level intermediate microassembly language. In SIMC, some high-level control constructs from the behavioral input language ADL of DIADES and GRAPH88 are preserved and can either be implemented in hardware or converted into lower-level microinstructions. An object-oriented HyperCard-based user interface has been designed to simplify user access to the system. >

Concurrent Two-Dimensional State Minimization and State Assignment of finite State Machines

Abstract: A generalization to the classical state minimization of a Finite State Machine (FSM) is described. The FSM is minimized here in two dimensions: numbers of both input symbols and internal states are minimized in an iterative sequence of input minimization and state minimization procedures. For each machine in the sequence of FSMs created by the algorithm an equivalent FSM is found that attempts 20 minimize the state assignment by selecting in each cell of the transition map one successor state from the set of successors. This approach leads to a partitioned realiration of the FSM with an input encoder. Our efficient branch-and-bound program, FMINI, produces an exact minimum result for each component minimization process and a globally quasi-minimum solution to the entire two-dimensional (2D) FSM combined process of state minimization and assignment.