Showing papers by "Marek Perkowski published in 1999"

Learning in hardware: architecture and implementation of an FPGA-based rough set machine

Abstract: The "Learning Hardware" approach proposed here involves creating a computational network based on feedback from the environment (for instance, positive and negative examples from the trainer), and realizing this network in an array of Field Programmable Gate Arrays (FPGAs). We advocate the approaches based on a "strong AI criterion"; for instance, the computational networks can be built based on Sum-of-Products logic minimization, functional logic decomposition, or Decision Tree construction. Here we propose the constructive induction approach to Learning Hardware based on Rough Sets Theory (RST). This approach allows the use of logical analysis to develop efficient hardware-realizable algorithms, and is contrasted with the popular Evolvable Hardware (EHW) approach in which learning/evolution is based on the genetic algorithm only. The RST algorithms have a natural high parallelism and high possible speed-ups. Using a fast prototyping tool, the DEC-PERLE-1 board based on an array of Xilinx FPGAs, we are developing a virtual SIMD processor that accelerates the learning (design) of optimized multi-valued logic nets.

Graph coloring algorithms for fast evaluation of Curtis decompositions

Abstract: Finding the minimum column multiplicity for a bound set of variables is an important problem in Curtis decomposition. To investigate this problem, we compared two graph coloring programs: one exact, and another one based on heuristics which can give, however, provably exact results on some types of graphs. These programs were incorporated into the multi-valued decomposer MVGUD. We proved that the exact graph coloring is not necessary for high-quality functional decomposers. Thus we improved by orders of magnitude the speed of the column multiplicity problem, with very little or no sacrifice of decomposition quality. Comparison of our experimental results with competing decomposers shows that for nearly all benchmarks our solutions are best and time is usually not too high.

Logic Synthesis for a Regular Layout

Abstract: New algorithms for generating a regular two-dimensional layout representation for multi-output, incompletely specified Boolean functions, called, Pseudo-Symmetric Binary Decision Diagrams (PSBDDs), are presented. The regular structure of the function representation allows accurate prediction of post-layout areas and delays before the layout is physically generated. It simplifies power estimation on the gate level and allows for more accurate power optimization. The theoretical background of the new diagrams, which are based on ideas from contact networks, and the form of decision diagrams for symmetric functions is discussed. PSBDDs are especially well suited for deep sub-micron technologies where the delay of interconnections limits the device performance. Our experimental results are very good and show that symmetrization of reallife benchmark functions can be done efficiently.

Evolvable hardware or learning hardware? induction of state machines from temporal logic constraints

Abstract: We advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraints solving, determinization, state machine minimization, structural mapping, functional decomposition of multi-valued logic functions and relations, and finally, FPGA mapping. In our approach, learning takes place on the level of constraint acquisition and functional decomposition rather than on the lower level of programming binary switches. Our learning strategy is based on the principle of Occam's Razor, facilitating generalization and discovery. We implemented several learning algorithms using DEC-PERLE-1 FPGA board.

Highly testable Boolean ring logic circuits

Abstract: In this paper we show how Boolean Ring logic, a group-based logic, leads to a circuit implementation that is highly testable. We develop Boolean Ring based expressions, which we call Generalized-Literal Boolean-Ring Sum-of-Products (GL-BRSOP) and Universal-Literal Boolean-Ring Sum-of-Products (UL-BRSOP) to represent (powers of 2)-valued MVL functions. Our BRSOPs: allow MVL functions to be implemented with vectors of binary AND and EXOR gates; allow the use of a binary logic fault model; and allow a time-multiplexed implementation that is highly testable and uses less redundant circuitry.

Constructive Induction Machines for Data Mining

Abstract: "Learning Hardware" approach involves creating a computational network based on feed­ back from the environment (for instance, positive and negative examples from the trainer), and realizing this network in an array of Field Programmable Gate Arrays (FPGAs). Compu­ tational networks can be built based on incremental supervised learning (Neural Net training) or global construction (Decision Tree design). Here we advocate the approach to Learning Hardware based on Constructive Induction methods of Machine Learning (ML) using multi­ valued functions. This is contrasted with the Evolvable Hardware (EHW) approach in which learning/evolution is based on the genetic algorithm only. Various approaches to supervised inductive learning for Data Mining and Machine Learning applications require fast operations on complex logic expressions and solving some NP-complete problems such as graph-coloring or set covering. They should be realized therefore in hardware to obtain the necessary speed-ups. Using a fast prototyping tool; the DEC-PERLE-l board based on an array of Xilinx FPGAs, we are developing virtual processors that accelerate the design and optimization of decomposed networks of arbitrary logic blocks.

Highly testable finite state machines based on EXOR logic

Abstract: It is well-known that AND/EXOR circuits are more easily testable than AND/OR circuits. Therefore, in this paper, we primarily propose to use AND/EXOR realizations for implementation of the combinational logic parts of finite state machines. Then, we investigate the effect of different state assignments (i.e. one-hot, grey-code, etc.) and that of using different types of registers (i.e. D-type, JK-type, etc) on the testability of finite state machines. As the basis of our measurements, we considered two easily testable AND/EXOR realizations; one for EXOR sum-of-products expressions and the other for generalized Reed-Muller expressions. We make comparisons of these realizations in terms of area and the number of test patterns as we change the state assignment and the type of registers. We also show that 2-level AND/EXOR realizations can yield less area than 2-level AND/OR realizations in the implementation of finite state machines.

ETDD-based synthesis of two-dimensional cellular arrays for multi-output incompletely specified Boolean functions

Abstract: Complex terms are logic expressions which can be mapped directly to cell arrays of cellular architecture devices such as Atmel 6000 series FPGAs. The paper presents an approach to the generation of complex terms for multi-output incompletely specified Boolean functions using EXOR ternary decision diagrams ETDDs. The expansions, Shannon, positive Davio and negative Davio, inherent in ETDDs, are employed to generate complex terms. While traversing the ETDD can be accomplished in a simple and efficient way for completely specified functions, the manipulation of ETDDs with don't care terms becomes very complex because the three expansions require different evaluations of the function. The changes made to the function due to don't cares in each expansion are analysed, and an approximation algorithm is presented with its applications to the minimisation of functions composed of complex terms.

TRACE: A Visual Software System to Explore Properties of Reed-Muller Movement Functions

Abstract: We present new experimental Windows 95/98/NT software for investigation of graph properties of boolean (in particular, Reed-Muller) logic with an equal number n of inputs and outputs (called movement functions). Realized at the input of an n-bit register, such functions create autonomous Finite State Machines (FSMs). TRACE software system allows the user to visualize State Transition Graphs (STGs) of the autonomous FSMs. Other features of TRACE help explore graph properties of function families. These families are produced by a generic function, differing from it only in the order of components, one operation, or one literal (this literal is complemented or replaced by another literal). The autonomous FSMs are used to implement economically next-state logic of realtime control units such as CPU controllers. A case study using TRACE to build economical, highly testable reversible counters based on linear Reed-Muller polynomials is given.