M
Mark G. Johnson
Researcher at SanDisk
Publications - 35
Citations - 4408
Mark G. Johnson is an academic researcher from SanDisk. The author has contributed to research in topics: Memory cell & Non-volatile memory. The author has an hindex of 21, co-authored 35 publications receiving 4408 citations. Previous affiliations of Mark G. Johnson include Rambus.
Papers
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Patent
Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
TL;DR: In this article, a very high density field programmable memory (FPM) is described. And the array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells.
Patent
Three-dimensional memory array and method of fabrication
N. Johan Knall,Mark G. Johnson +1 more
TL;DR: In this paper, a multi-level memory array employing rail-stacks is described, which include a conductor and semiconductor layers, separated by an insulating layer used to form antifuses.
Patent
Dense arrays and charge storage devices, and methods for making same
Thomas H. Lee,Vivek Subramanian,James M. Cleeves,Andrew J. Walker,Christopher J. Petti,Igor G. Kouznetzov,Mark G. Johnson,Paul M. Farmwald,Brad Herner +8 more
TL;DR: In this article, a monolithic three dimensional array of charge storage devices, including a plurality of device levels, is provided, where at least one surface between two successive device levels is planarized by chemical mechanical polishing.
Patent
Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
TL;DR: In this paper, a nonvolatile memory array with at least one driver circuit and a substrate is described. But the driver circuit is not located in a bulk monocrystalline silicon substrate, and the at least driver circuit may be located in silicon on insulator substrate or in a compound semiconductor substrate.
Patent
Delay locked loop circuitry for clock delay adjustment
Kevin S. Donnelly,Pak Shing Chau,Mark A. Horowitz,Thomas H. Lee,Mark G. Johnson,Benedict Lau,Leung Yu,Bruno W. Garlepp,Yiu-Fai Chan,Jun Kim,Chanh Tran,Donald C. Stark +11 more
TL;DR: In this paper, a delay-locked loop (320, 350) was proposed for generating a predetermined phase relationship between a pair of clocks (300, 310), where a phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560) based on the phase comparison.