Patent
Three-dimensional memory array and method of fabrication
N. Johan Knall,Mark G. Johnson +1 more
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TLDR
In this paper, a multi-level memory array employing rail-stacks is described, which include a conductor and semiconductor layers, separated by an insulating layer used to form antifuses.Abstract:
A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.read more
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Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
TL;DR: In this article, a very high density field programmable memory (FPM) is described. And the array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells.
Patent
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Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
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Semiconductor device and structure
Zvi Or-Bach,Brian Cronquist +1 more
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
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Method for fabrication of a semiconductor device and structure
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
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NAND flash memory controller exporting a NAND interface
TL;DR: A NAND controller for interfacing between a host device and a flash memory device (e.g., a NAND flash memory devices) fabricated on a flash die is disclosed in this paper.
References
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Patent
Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
TL;DR: In this article, a very high density field programmable memory (FPM) is described. And the array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells.
Patent
Programmable cell for use in programmable electronic arrays
TL;DR: An improved programmable cell for use in programmable electronic arrays such as PROM devices, logic arrays, gate arrays and die interconnect arrays is presented in this paper, where the cells have a highly nonconductive state settable and non-resettable into a highly conductive state.
Patent
Three-dimensional read-only memory
TL;DR: A read-only memory structure, having a three dimensional arrangement of memory elements, is described in this paper, where memory elements are partitioned into multiple memory levels and each memory level is stacked on top of another.
Patent
Programmable semiconductor structures and method for using the same
TL;DR: In this article, a programmable device can be made with semiconductor layers which form two series coupled back-to-back diodes, each of which can be selectively programmed to lose its rectifying feature.
Journal ArticleDOI
Three-dimensional IC trends
TL;DR: In this article, the authors proposed a 3D IC architecture with three active layers, and the technical issues for realizing practical 3-D IC, i.e., the technology for fabricating high-quality SOI crystal on complicated surface topology, crosstalk of the signals between the stacked layers, total power consumption and cooling of the chip, are discussed.