An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Methods and apparatus for measuring analytes

Methods and apparatuses relating to large scale FET arrays for analyte detection and measurement are provided. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes.

Methods and apparatus for detecting molecular interactions using FET arrays

Aspects of the subject disclosure may include, for example, receiving, by a feed point of a dielectric antenna, electromagnetic waves from a dielectric core coupled to the feed point without an electrical return path, where at least a portion of the dielectric antenna comprises a conductive surface, directing, by the feed point, the electromagnetic waves to a proximal portion of the dielectric antenna, and radiating, via an aperture of the dielectric antenna, a wireless signal responsive to the electromagnetic waves being received at the aperture. Other embodiments are disclosed.

Method and apparatus for coupling an antenna to a device

A surgical instrument includes a failure response system with a first circuit configured to detect a first operational error of the powered surgical stapling and cutting instrument, and a control circuit configured to activate a first failure response mode if the first operational error is detected.

Surgical instrument with multiple failure response modes

Delay locked loops (320, 350) for generating a predetermined phase relationship between a pair of clocks (300, 310). A first delay-locked loop (320) includes delay elements arranged in a chain, the chain receiving an input clock (300) and generating, from each delay element, a set of phase vectors (330), each shifted a unit delay from the adjacent vector. The first delay-locked loop (320) adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors (330) span a predetermined phase shift of the input clock (300). A second delay-locked loop (350) selects, from the first delay-locked loop (320), a pair of phase vectors which brackets the phase of an input clock (300). A phase interpolator (560) receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector (590) compares the delayed output clock with the input clock and adjusts the phase interpolator (560), based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock (410). As a result, there is a predetermined phase relationship being the amount of delay between the output clock (640) and the delayed output clock (360).

Delay locked loop circuitry for clock delay adjustment

A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.

Integrating receiver with precharge circuitry

A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Method and apparatus for evaluating and optimizing a signaling system

Low-latency equalization mechanisms for multi-PAM communication systems are disclosed that reduce delay and complexity in signal correction mechanisms. The equalization mechanisms tap into input signals for a multi-PAM signal driver, and compensate for attenuation along a signal transmission line, crosstalk between adjacent lines, and signal reflections due to impedance discontinuities along the line.

Low-latency equalization in multi-level, multi-line communication systems

Circuitry (500, Fig. 4) for adjusting the phase of an incoming periodic signal (Clk_In), typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry (500) has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains (410 and 510) receiving complementary clocks (Clk_In and Clk_InB). Phase adjustment circuitry comprises a delay chain having a plurality of taps (T0-Tn), a boundary detector (490) for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry (450) for selecting one of the taps from the delay chain based on the boundary detector output (495) and the selection circuitry input (OC) such that the selected tap is the desired phase adjustment of the incoming signal and that the delay of the incoming signal is adjustable across its phase boundaries. Phase interpolation (348 in Fig. 3) between the taps of the delay chain is employed to increase the resolution of the adjustment to the periodic signal. Duty cycle correction (Fig. 13) of the input clock and the selected output clock is employed to improve accuracy.

Pak Shing Chau

Papers

Delay locked loop circuitry for clock delay adjustment

Integrating receiver with precharge circuitry

Method and apparatus for evaluating and optimizing a signaling system

Low-latency equalization in multi-level, multi-line communication systems

Circuitry for the delay adjustment of a clock signal