Martin Foltin

TL;DR: The Programmable Ultra-efficient Memristor-based Accelerator (PUMA) as mentioned in this paper enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads.

TL;DR: A memristor-based annealing system that uses an analogue neuromorphic architecture based on a Hopfield neural network can solve non-deterministic polynomial-time (NP)-hard max-cut problems in an approach that is potentially more efficient than current quantum, optical and digital approaches.

TL;DR: The Programmable Ultra-efficient Memristor-based Accelerator (PUMA) is presented which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads.

TL;DR: In this paper, the analog content-addressable memory (CA-MAM) concept and circuit is proposed to reduce the area and power consumption by utilizing the analog conductance tunability of memristors.

TL;DR: PANTHER, an ISA-programmable training accelerator with compiler support, is developed and can be integrated into other accelerators in the literature to enhance their efficiency.