In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraint-driven placement problem.

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Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The method is based on a novel symmetry computation method, introducing the structural signal flow graph. Five types of proximity, matching and symmetry constraints are determined. According to the priority of the constraint types, a constraint requirement graph and a hierarchical partitioning of the circuit into matching, proximity and symmetry groups is then automatically computed. Based on experimental results with a state-of-the-art placement tool, we show that the new approach generates more placement rules and can lead to better circuit performance and parametric yield according to post-layout simulation.

Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits

A flow is presented for the automatic synthesis of an analog circuit layout based on a schematic and a list of circuit design parameter values. The flow is driven by design, placement, and routing constraints-no layout template is necessary. Every possible layout for each device in the circuit is investigated; the layouts with the best geometric features and smallest quantization error (due to manufacturing grid alignment) are kept. For circuit placement, a complete enumeration of possible circuit placements, limited only by usual constraints of symmetry, proximity, and common centroid, is performed. Out of this enumeration a final circuit placement is selected and routed. The new flow is integrated with a deterministic nonlinear optimization algorithm to perform layout-driven circuit sizing; layouts are synthesized during both gradient approximation and next step determination. Layout-driven circuit sizing was applied to two example circuits. Sizing of the first circuit example took 8× the amount of CPU time needed for traditional circuit sizing, but remained feasible at 2.1 h of wall clock time on a contemporary workstation.

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Constraint-Based Layout-Driven Sizing of Analog Circuits

This paper presents analog layout automation efforts under the ALIGN ("Analog Layout, Intelligently Generated from Netlists") project for fast layout generation using a modular approach based on a mix of algorithmic and machine learning-based tools. The road to rapid turnaround is based on an approach that detects structure and hierarchy in the input netlist and uses a grid based philosophy for layout. The paper provides a view of the current status of the project, challenges in developing open-source code with an academic/industry team, and nuts-and-bolts issues such as working with abstracted PDKs, navigating the "wall" between secured IP and open-source software, and securing access to example designs.

INVITED: ALIGN – Open-Source Analog Layout Automation from the Ground Up

Analog IC placement is typically a manual process that requires strong experience and trial-and-error iterations as it produces a large impact to circuit performance in a complicated manner. Although automatic analog placement has been studied for decades, existing methods are inadequate for achieving performance comparable with manual designs. In this work, a customized graph neural network model is developed for predicting the impact of placement on circuit performance. Knowledge obtained by such a model can be transferred among different topologies of the same circuit type. Simulation results show that the proposed model is superior to a recent CNN-based work in terms of both accuracy and knowledge transfer. It also outperforms a plug-in use of graph attention network. The proposed model is further applied in analog IC placement and achieves performance similar to manual designs.

A customized graph neural network model for guiding analog IC placement

The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The practically relevant solution space is thereby enumerated quasi-complete. The sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. The result of Plantage is the Pareto front of placements with respect to different aspect ratios. The whole approach is deterministic, in contrast to existing analog placement algorithms.

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Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions

This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.

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Analog layout synthesis: recent advances in topological approaches

This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement.The netlist, a library of building blocks and a symmetry analysis are the basis to determine a constraint requirement graph, which comprises five types of proximity, matching and symmetry constraints. According to the priority of the constraint types, a hierarchical partitioning of the circuit into matching, proximity and symmetry groups is then automatically computed and forwarded to a state-of-the-art placement tool.Based on experimental results, we show that the new approach generates more placement rules and leads to better circuit performances according to post-layout simulation compared to a commercial approach.

Automatic generation of hierarchical placement rules for analog integrated circuits

For analog integrated circuits, generating a layout represents the bottleneck in the design flow. To automate the layout step, it is necessary to create placements with respect to various constraints automatically. Since the constraints can be numerous, an automatic generation of the layout constraints is crucial as well. In this chapter, a comprehensive and deterministic methodology for analog layout design automation is presented. An approach to automatically generate constraints for analog circuits is described. It recognizes building blocks, e.g., current mirrors, and symmetry conditions in the circuit and, with prioritized rules, generates constraints and hierarchy information. Then, a placement algorithm, called “Plantage”, is presented, which is capable to handle all relevant constraints. It uses the hierarchy information of the previous step to guide an enumeration process. Plantage calculates a Pareto front of placements with respect to different aspect ratios. The results show high quality in terms of area and postlayout circuit performance.

Martin Strasser

Papers

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions

Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits

Analog layout synthesis: recent advances in topological approaches

Automatic generation of hierarchical placement rules for analog integrated circuits

Deterministic Analog Placement by Enhanced Shape Functions