A computer implemented method on a computer readable media is provided for determining the source of a problem in a complex system of managed components based upon symptoms. The problem source identification process is split into different activities. Explicit configuration non-specific representations of types of managed components, their problems, symptoms and the relations along which the problems or symptoms propagate are created that can be manipulated by executable computer code. A data structure is produced for determining the source of a problem by combining one or more of the representations based on information of specific instances of managed components in the system. Computer code is then executed which uses the data structure to determine the source of the problem from one or more symptoms.

Apparatus and method for event correlation and problem reporting

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Diagnosis and reliable design of digital systems

A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

Test pattern compression for an integrated circuit test environment

A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

Method and apparatus for selectively compacting test responses

A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Decompressor/PRPG for applying pseudo-random and deterministic test patterns

A plurality of first flip-flop circuits are provided having outputs connected respectively to inputs of a logic circuit. During a test mode, scan data is first loaded into the flip-flop circuits to activate desired logical paths in the logic circuit and subsequently a pulse is scanned across the first flip-flop circuits to cause successive reversals to occur in the stored scan data. As a result, test signals can propagate through the activated logical paths. Connected to the outputs of the logic circuit are a plurality of second flip-flop circuits which are configured into a linear feedback shift register during the test mode to enable a test circuit to observe its serial output to determine the dynamic performance of the logic circuit.

LSI chip with scanning circuitry for generating reversals along activated logical paths

A prototype version of a new switch-level fault simulator for digital MOS IC's is described. The simulation program, which is called CSASIM, analyzes CSA (connector-switch-attenuator) circuit models using multiple logic values. A novel method of signal evaluation is employed, based on the super-position of bidirectional static and dynamic signals. CSASIM also allows efficient simulation of many different fault types, including stuck-at-constant, open-circuit, short-circuit, and delay faults. The internal structure and fault-simulation mechanisms of the simulator are discussed in this paper.

An Experimental MOS Fault Simulation Program CSASIM

Self-diagnosable integrated circuit device capable of testing sequential circuit elements

The authors describe scan path, NEC's implementation of the scan design approach to design for testability. Designers at NEC have found that scan path greatly contributes to the reduced testing and maintenance cost of their products. The authors discuss several implementations of scan design and compare four implementations, including two scan-path techniques. >

Masato Kawai

Papers

LSI chip with scanning circuitry for generating reversals along activated logical paths

An Experimental MOS Fault Simulation Program CSASIM

Self-diagnosable integrated circuit device capable of testing sequential circuit elements

Scan design at NEC

A High Level Test Pattern Generation Algorithm.