Masaya Yamasaki

TL;DR: In this article, the authors proposed an algorithm based on classical mechanics, which is obtained by modifying a previously proposed algorithm called simulated bifurcation, to achieve not only high speed by parallel computing but also high solution accuracy for problems with up to one million binary variables.

TL;DR: A scale-out architecture for Ising machines that provides enlarged machine sizes and enhanced processing speeds by using multiple connected chips and relies on an autonomous synchronization mechanism that is implemented in the information exchange processes between neighbouring chips and leads to scalability of computational throughput.

TL;DR: In this article, the interpolated frame generating method is proposed to insert a new frame inserted between sequential frames, by using a plurality of input frame images, which comprises first detecting of detecting at least one potential motion vector by block matching between the input frames, using a first block of a fixed size, second detecting of finding a motion vector between the frames, and a second block having a size variable within a range larger than that of the first block.

TL;DR: In this paper, an interpolation frame generating method performs motion detection processing using two blocks having different sizes, and adopts a motion vector detected by a smaller block under normal conditions.

TL;DR: In this article, a frame interpolating circuit including detecting unit which detects first frame image and second frame image from an input image signal and compares both the images with each other to detect a plurality of motion vectors in a pluralityof blocks obtained by dividing the frame into blocks.