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Masayuki Ikebe

Researcher at Hokkaido University

Publications -  121
Citations -  710

Masayuki Ikebe is an academic researcher from Hokkaido University. The author has contributed to research in topics: CMOS & Pixel. The author has an hindex of 11, co-authored 108 publications receiving 549 citations. Previous affiliations of Masayuki Ikebe include Dai Nippon Printing.

Papers
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Journal ArticleDOI

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

TL;DR: In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binary/ternaty neural network, improves the energy efficiency dramatically.
Proceedings ArticleDOI

BRein memory: A 13-layer 4.2 K neuron/0.8 M synapse binary/ternary reconfigurable in-memory deep neural network accelerator in 65 nm CMOS

TL;DR: A versatile reconfigurable accelerator for binary/ternary deep neural networks (DNNs) is presented, which features a massively parallel in-memory processing architecture and stores varieties of binary/ Sternary DNNs with a maximum of 13 layers, 4.2 K neurons, and 0.8 M synapses on chip.
Journal ArticleDOI

A Wide-Dynamic-Range Compression Image Sensor With Negative-Feedback Resetting

TL;DR: In this paper, the authors proposed a wide-dynamic-range compression (WDRC) sensor using a negative feedback technique to set any intermediate voltage into photodiode (PD) capacitance in the pixel circuit.
Proceedings ArticleDOI

60-GHz, 9-µW wake-up receiver for short-range wireless communications

TL;DR: An ultra-low power 60-GHz band wake-up receiver designed and fabricated with a 0.18-μm RF CMOS low-cost technology and successfully operates with power consumption of only 9 μW from a 1.5-V supply and a high sensitivity of -68 dBm.
Patent

Integral A/D converter and CMOS image sensor

TL;DR: The integral type AD converter includes a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal, a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configures to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp wave form to the inversion of the outputting from the delay adjusting circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of signal when the output of the delay