[신간의 별자리x] 우리/미술, 그리고 ‘슬픔의 박물관’

The specification discloses a method of doing business over the public Internet, particularly, a method which enables access to legacy management tools used by a telecommunications enterprise in the management of the enterprise business to the enterprise customer, to enable the customer to more effectively manage the business conducted by the customer through the enterprise, this access being provided over the public Internet. This method of doing business is accomplished with one or more secure web servers which manage one or more secure client sessions over the Internet, each web server supporting secure communications with the client workstation; a web page backplane application capable of launching one or more management tool applications used by the enterprise. Each of the management tool applications provide a customer interface integrated within said web page which enables interactive Web/Internet based communications with the web servers; each web server supports communication of messages entered via the integrated customer interface to one or more remote enterprise management tool application servers which interact with the enterprise management tool applications to provide associated management capabilities to the customer.

Integrated business system for web based telecommunications management

The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A double firewalled system is disclosed for protecting remote enterprise servers that provide communication services to telecommunication network customers from unauthorized third parties. A first router directs all connection requests to one or more secure web servers, which may utilize a load balancer to efficiently distribute the session connection load among a high number of authorized client users. On the network side of the web servers, a second router directs all connection requests to a dispatcher server, which routes application server calls to a proxy server for the application requested. A plurality of data security protocols are also employed. The protocols provide for an identification of the user, and an authentication of the user to ensure the user is who he/she claims to be and a determination of entitlements that the user may avail themselves of within the enterprise system. Session security is described, particularly as to the differences between a remote user's copper wire connection to a legacy system and a user's remote connection to the enterprise system over a “stateless” public Internet, where each session is a single transmission, rather than an interval of time between logon and logoff, as is customary in legacy systems.

Secure server architecture for web based data management

A dynamic RAM is provided using a sense amplifier compensating for the disparities of characteristics for paired MOSFET's. With this arrangement parasitic capacitance of the bit lines can be increased to be at least 20 times the capacitance of the memory cells. Each bit line is bisected by a switch MOSFET and is disconnected thereby as needed. A plurality of sets of memory arrays are furnished, each including a switch MOSFET for interconnecting common source lines to which the sense amplifier is connected. This permits recycling of the charges of the common source lines.

Dynamic RAM and information processing system using the same

A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.

Semiconductor device, such as a synchronous DRAM, including a control circuit for reducing power consumption

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-/spl mu/m CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71/spl times/1.20 /spl mu/m/sup 2/, and the chip size is 15.91/spl times/9.06 mm/sup 2/. A typical access time under 3.3 V power supply voltage is 29 ns.

A 29-ns 64-Mb DRAM with hierarchical array architecture

A semiconductor integrated circuit device having a DRAM consisting of memory cells, comprises; a first conductive film deposited over the main surface of a semiconductor substrate and used to form a gate electrode of a memory cell selection MISFET; a second conductive film deposited over the first conductive film and used to form bit lines to transfer data of a memory cell to a sense amplifier; a third conductive film deposited over the second conductive film and used to form a storage node of a capacitor; a fourth conductive film deposited over the third conductive film and used to form a plate electrode of the capacitor; and a fifth conductive film deposited over the fourth conductive film and used to form an interconnect, wherein a transistor in a direct peripheral circuit arranged close to a memory array is electrically connected, through a pad layer formed of the third conductive film, to the interconnection of the fifth conductive film deposited over the fourth conductive film, thereby allowing the aspect ratio of the contact hole formed over the pad layer to be reduced.

Semiconductor integrated circuit device and a manufacturing method thereof

A dynamic RAM enhanced in integration and storage capacity, a method of setting a plate voltage of the dynamic RAM, and an information processing system reduced in size and enhanced in performance are provided. The plate voltage is set such that a leakage current of an information storage capacitor when a bit line voltage is positive relative to the plate voltage is made substantially equal to a leakage current of the capacitor when the bit line voltage is negative relative to the plate voltage. For this plate voltage setting, a plate voltage generating circuit is provided with an output voltage adjusting capability. A monitoring capacitor is formed on the same semiconductor wafer on which the information storage capacitor is formed. This monitoring capacitor is formed by a same method by which the information storage capacitor is formed, and is made of a same material of which the information storage capacitor is made. The monitoring capacitor is tested in a wafer probing process. Based on a measurement result, the plate voltage is set to an optimum level. The information processing system is constituted with the dynamic RAM as its memory device having the optimum plate voltage.

Masayuki Nakamura

Papers

Dynamic RAM and information processing system using the same

Semiconductor device, such as a synchronous DRAM, including a control circuit for reducing power consumption

A 29-ns 64-Mb DRAM with hierarchical array architecture

Semiconductor integrated circuit device and a manufacturing method thereof

Dynamic RAM, dynamic RAM plate voltage setting method, and information processing system