Energy consumption has become a major constraint on the capabilities of computer systems. In large systems the energy consumed by Dynamic Random Access Memories (DRAM) is a significant part of the total energy consumption. It is possible to calculate the energy consumption of currently available DRAMs from their datasheets, but datasheets don’t allow extrapolation to future DRAM technologies and don’t show how other changes like increasing bandwidth requirements change DRAM energy consumption. This paper first presents a flexible DRAM power model which uses a description of DRAM architecture, technology and operation to calculate power usage and verifies it against datasheet values. Then the model is used together with assumptions about the DRAM roadmap to extrapolate DRAM energy consumption to future DRAM generations. Using this model we evaluate some of the proposed DRAM power reduction schemes.

Understanding the Energy Consumption of Dynamic Random Access Memories

Linear regulators are critical analog blocks that shield a system from fluctuations in supply rails and the importance of determining their power supply rejection (PSR) performance is magnified in SoC systems, given their inherently noisy environments. In this work, a simple, intuitive, voltage divider model is introduced to analyze the PSR of linear regulators, from which design guidelines for obtaining high PSR performance are derived. The PSR of regulators that use PMOS output stages for low drop-out (LDO), crucial for modern low-voltage systems, is enhanced by error amplifiers which present a supply-correlated ripple at the gate of the PMOS pass device. On the other hand, amplifiers that suppress the supply ripple at their output are optimal for NMOS output stages since the source is now free from output ripple. A better PSR bandwidth, at the cost of dc PSR, can be obtained by interchanging the amplifiers in the two cases. It has also been proved that the dc PSR, its dominant frequency breakpoint (where performance starts to degrade), and three subsequent breakpoints are determined by the dc open-loop gain, error amplifier bandwidth, unity-gain frequency (UGF) of the system, output pole, and ESR zero, respectively. These results were verified with SPICE simulations using BSIM3 models for the TSMC 0.35 /spl mu/m CMOS process from MOSIS.

Analysis and design of monolithic, high PSR, linear regulators for SoC applications

A 256-Mb SDRAM (245.7 mm/sup 2/) has been developed using (1) a high cell occupation ratio (60.2%) array design for chip size reduction and a high yield, (2) a prefetched pipeline scheme (PPS) using a first-in first-out (FIFO) buffer with parallel serial converter for 250-MHz clock frequency operation, and (3) a synchronous mirror delay (SMD) circuit for 2.5-ns clock access and low standby current.

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper introduces CACTI-3DD, the first architecture-level integrated power, area, and timing modeling framework for 3D die-stacked off-chip DRAM main memory. CACTI-3DD includes TSV models, improves models for 2D off-chip DRAM main memory over current versions of CACTI, and includes 3D integration models that enable the analysis of a full spectrum of 3D DRAM designs from coarse-grained rank-level 3D stacking to bank-level 3D stacking. CACTI-3DD enables an in-depth study of architecture-level tradeoffs of power, area, and timing for 3D die-stacked DRAM designs. We demonstrate the utility of CACTI-3DD in analyzing design trade-offs of emerging 3D die-stacked DRAM main memories. We find that a coarse-grained 3D DRAM design that stacks canonical DRAM dies can only achieve marginal benefits in power, area, and timing compared to the original 2D design. To fully leverage the huge internal bandwidth of TSVs, DRAM dies must be re-architected, and system implications must be considered when building 3D DRAMs with redesigned 2D planar DRAM dies. Our results show that the 3D DRAM with re-architected DRAM dies achieves significant improvements in power and timing compared to the coarse-grained 3D die-stacked DRAM.

CACTI-3DD: architecture-level modeling for 3D die-stacked DRAM main memory

SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback-cutoff (DAFC) scheme to enlarge the write margin and dynamic-read-decoupled (DRD) scheme to prevent read-disturb for achieving deep subthreshold operation. A 30 mV negative-pumped wordline scheme is employed to suppress bitline leakage current. The fabricated 90 nm 32 Kb 9T-SRAM macro achieves 130 mV VDDmin. All the 32 Kb 9T cells are stable across read and write operations when operated at 105 mV.

A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications

A precise on-chip voltage generator for gigascale DRAM's with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-/spl mu/m process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and V/sub BB/ bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAM's.

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-/spl mu/m CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71/spl times/1.20 /spl mu/m/sup 2/, and the chip size is 15.91/spl times/9.06 mm/sup 2/. A typical access time under 3.3 V power supply voltage is 29 ns.

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 256 K*4 FIFO (first-in-first-out) CMOS memory with 20-ns access time and 30-ns cycle time is described. To accomplish full static and asynchronous operation, signal synchronizer and arbiter circuits have been developed and implemented into the device. A pair of 120-word*4-bit static memories are furnished to provide 20-ns data access from the very first read cycle. The average current measured at 30-ns read/write operation and the standby current are typically 23 and 1.2 mA, respectively. >

A 20-ns 256 K*4 FIFO memory

We have designed a precise on-chip voltage generator for giga-scale DRAMs with a negative word-line scheme. It combines a charge-pump regulator and a series-pass regulator, and includes a positive/negative offset voltage generator that uses a band-gap generator with a differential amplifier. The noise on a low-voltage word-line is suppressed to below 30 mV for the word-line transient and VBB bouncing. A DC voltage error of less than 6% without trimming is also achieved.

http://ieeexplore.ieee.org/iel4/5639/15113/00688013.pdf

T. Tachibana

Papers

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 20-ns 256 K*4 FIFO memory

A precise on-chip voltage generator for a giga-scale DRAM with a negative word-line scheme