Approximate computing trades off computation quality with effort expended, and as rising performance demands confront plateauing resource budgets, approximate computing has become not merely attractive, but even imperative. In this article, we present a survey of techniques for approximate computing (AC). We discuss strategies for finding approximable program portions and monitoring output quality, techniques for using AC in different processing units (e.g., CPU, GPU, and FPGA), processor components, memory technologies, and so forth, as well as programming frameworks for AC. We classify these techniques based on several key characteristics to emphasize their similarities and differences. The aim of this article is to provide insights to researchers into working of AC techniques and inspire more efforts in this area to make AC the mainstream computing approach in future systems.

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A Survey of Techniques for Approximate Computing

This paper presents an ultra-low power batteryless energy harvesting body sensor node (BSN) SoC fabricated in a commercial 130 nm CMOS technology capable of acquiring, processing, and transmitting electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG) data. This SoC utilizes recent advances in energy harvesting, dynamic power management, low voltage boost circuits, bio-signal front-ends, subthreshold processing, and RF transmitter circuit topologies. The SoC is designed so the integration and interaction of circuit blocks accomplish an integrated, flexible, and reconfigurable wireless BSN SoC capable of autonomous power management and operation from harvested power, thus prolonging the node lifetime indefinitely. The chip performs ECG heart rate extraction and atrial fibrillation detection while only consuming 19 μW, running solely on harvested energy. This chip is the first wireless BSN powered solely from a thermoelectric harvester and/or RF power and has lower power, lower minimum supply voltage (30 mV), and more complete system integration than previously reported wireless BSN SoCs.

A Batteryless 19 $\mu$ W MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications

Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level reconfigurable abstractions. Both fine-grain and coarse-grain architectures (e.g. CGRAs) traditionally require low level programming and suffer from long compilation times. We address both challenges with Plasticine, a new spatially reconfigurable architecture designed to efficiently execute applications composed of parallel patterns. Parallel patterns have emerged from recent research on parallel programming as powerful, high-level abstractions that can elegantly capture data locality, memory access patterns, and parallelism across a wide range of dense and sparse applications.We motivate Plasticine by first observing key application characteristics captured by parallel patterns that are amenable to hardware acceleration, such as hierarchical parallelism, data locality, memory access patterns, and control flow. Based on these observations, we architect Plasticine as a collection of Pattern Compute Units and Pattern Memory Units. Pattern Compute Units are multi-stage pipelines of reconfigurable SIMD functional units that can efficiently execute nested patterns. Data locality is exploited in Pattern Memory Units using banked scratchpad memories and configurable address decoders. Multiple on-chip address generators and scatter-gather engines make efficient use of DRAM bandwidth by supporting a large number of outstanding memory requests, memory coalescing, and burst mode for dense accesses. Plasticine has an area footprint of 113 mm2 in a 28nm process, and consumes a maximum power of 49 W at a 1 GHz clock. Using a cycle-accurate simulator, we demonstrate that Plasticine provides an improvement of up to 76.9x in performance-per-Watt over a conventional FPGA over a wide range of dense and sparse applications.

https://dl.acm.org/doi/pdf/10.1145/3079856.3080256

Plasticine: A Reconfigurable Architecture For Parallel Paterns

https://hal.archives-ouvertes.fr/hal-01050920/document

Proton exchange membrane fuel cell degradation prediction based on Adaptive Neuro-Fuzzy Inference Systems .

Many applications that can take advantage of accelerators are amenable to approximate execution. Past work has shown that neural acceleration is a viable way to accelerate approximate code. In light of the growing availability of on-chip field-programmable gate arrays (FPGAs), this paper explores neural acceleration on off-the-shelf programmable SoCs. We describe the design and implementation of SNNAP, a flexible FPGA-based neural accelerator for approximate programs. SNNAP is designed to work with a compiler workflow that configures the neural network's topology and weights instead of the programmable logic of the FPGA itself. This approach enables effective use of neural acceleration in commercially available devices and accelerates different applications without costly FPGA reconfigurations. No hardware expertise is required to accelerate software with SNNAP, so the effort required can be substantially lower than custom hardware design for an FPGA fabric and possibly even lower than current “C-to-gates” high-level synthesis (HLS) tools. Our measurements on a Xilinx Zynq FPGA show that SNNAP yields a geometric mean of 3.8× speedup (as high as 38.1×) and 2.8× energy savings (as high as 28 x) with less than 10% quality loss across all applications but one. We also compare SNNAP with designs generated by commercial HLS tools and show that SNNAP has similar performance overall, with better resource-normalized throughput on 4 out of 7 benchmarks.

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SNNAP: Approximate computing on programmable SoCs via neural acceleration

Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-V DD, multi-V DD, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort.

Flexible Circuits and Architectures for Ultralow Power

Massively parallel computation in GPUs significantly boosts performance of compute-intensive applications but creates power and thermal issues that limit further performance scaling. This paper demonstrates significant GPGPU power savings by relaxing application accuracy requirements and enabling the use of low power imprecise hardware (IHW). A synthesized set of novel imprecise floating point arithmetic units is presented. GPGPU-Sim and GPUWattch are used to estimate impacts of IHW units on output quality and system-level power consumption, providing a quality-power tradeoff model for application-specific optimization. Experimental results for a 45 nm process show up to 32% power savings with negligible impacts on output quality.

Low Power GPGPU Computation with Imprecise Hardware

Corrosion of aircraft and rotorcraft costs the US military billions of dollars annually, and is by far the largest single maintenance cost driver for Navy and Marine Corps airframes. The various forms of localized corrosion, such as pitting corrosion, crevice corrosion, exfoliation, and environment assisted cracking, are particularly destructive and frequently occur without any outward signs of damage. To maintain acceptable risk levels, costly schedule based inspection and maintenance practices are used. In order to move away from schedule based maintenance and enable condition based maintenance techniques, a miniature corrosion monitoring smart sensor network to support diagnostics and prognostics for aircraft health management is being developed. The development of an ultra-low power, wireless, embedded corrosion monitoring system based on the IEEE 1451.X open architecture for smart transducers will be discussed in this paper. This system, funded through a NAVAIR Phase II SBIR, is capable of monitoring, recording, and analyzing data from environmental and corrosivity sensors for the purpose of aircraft health management. This paper will present the use of a standard network architecture consisting of transducer interface modules (TIMs) and network capable application processors (NCAPs), allowing for ease of system integration and plug-and-play simplicity. The hardware and software designs, relying on ultra-low power components and embedded energy conservation algorithms, will be presented. This low-power approach to aircraft corrosion and health monitoring is ideal for integration with energy harvesting techniques, giving rise to a self-contained, self-sustaining sensor network. Finally, corrosion modeling and embedded algorithm development based on data fusion from both commercial off the shelf (COTS) and novel, developmental sensors will be discussed and shown to be powerful diagnostic and prognostic tools. 1 2

Development of a wireless miniaturized smart sensor network for aircraft corrosion monitoring

The energy efficiency of a CMOS architecture processing dynamic workloads directly affects its ability to provide long battery lifetimes while maintaining required application performance. Existing scalable architecture design approaches are often limited in scope, focusing either only on circuit-level optimizations or architectural adaptations individually. In this paper, we propose a circuit/architecture co-design methodology called Panoptic Dynamic Voltage Scaling (PDVS) that makes more efficient use of common circuit structures and algorithm-level processing rate control. PDVS expands upon prior work by using multiple component-level PMOS header switches to enable fine-grained rate control, allowing efficient dithering among statically scheduled algorithms with sub-block energy savings. This way, PDVS is able to achieve a wide variety of processing rates to match incoming workload as closely as possible, while each iteration takes less energy to process than on architectures with coarser levels of rate control. Measurements taken from a fabricated 90nm test chip characterize both savings and overheads and are used to inform PDVS synthesis decisions. Results show that PDVS consumes up to 34% and 44% less energy than Multi-VDD and Single-VDD systems, respectively.

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Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design

Recent imprecise hardware (IHW) design methodologies present opportunities for achieving gains in nonfunctional efficiency design metrics by allowing errors in computation within error tolerant application domains. This work presents a novel imprecise Error Tolerant Balancing Adder (ETBA) design - an augmentation of the ETAIIM IHW adder that reduces errors by introducing a balance block that detects and corrects carry chain inconsistencies in the ETAIIM but operates off the critical path. Furthermore, this work identifies a common class of killer inputs with high error rates for IHW adders, and demonstrates the ETBA's resilience to these errors. A JPEG decompression case study reveals a 24% reduction in ETBA addition energy-delay product compared to a Kogge-Stone adder with only a 0.2% reduction in SSIM image quality.

Mateja Putic

Papers

Flexible Circuits and Architectures for Ultralow Power

Low Power GPGPU Computation with Imprecise Hardware

Development of a wireless miniaturized smart sensor network for aircraft corrosion monitoring

Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design

Balancing Adder for error tolerant applications