S
Sudhanshu Khanna
Researcher at Texas Instruments
Publications - 52
Citations - 716
Sudhanshu Khanna is an academic researcher from Texas Instruments. The author has contributed to research in topics: State (computer science) & Dynamic voltage scaling. The author has an hindex of 14, co-authored 52 publications receiving 683 citations. Previous affiliations of Sudhanshu Khanna include University of Virginia.
Papers
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Journal ArticleDOI
Flexible Circuits and Architectures for Ultralow Power
TL;DR: This paper presents a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points.
Proceedings ArticleDOI
An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at V DD =0V with <400ns wakeup and sleep transitions
Steven Bartling,Sudhanshu Khanna,Michael Patrick Clinton,Scott R. Summerfelt,John A. Rodriguez,Hugh P. McAdams +5 more
TL;DR: A non-volatile logic (NVL)-based SoC is demonstrated that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400ns to restore the system state upon power-up.
Proceedings ArticleDOI
Sub-threshold circuit design with shrinking CMOS devices
TL;DR: It is shown that special strategies are needed for different categories of sub-threshold circuits and to combat random variation and minimize energy for nodes below 45nm, it is necessary to reduce variation and suppress leakage current.
Journal ArticleDOI
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at ${\rm VDD}=$ 0 V Achieving Zero Leakage With ${ 400-ns Wakeup Time for ULP Applications
Sudhanshu Khanna,Steven Bartling,Michael Patrick Clinton,Scott R. Summerfelt,John A. Rodriguez,Hugh P. McAdams +5 more
TL;DR: This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up.
Journal ArticleDOI
Impact of circuit assist methods on margin and performance in 6T SRAM
Randy W. Mann,Jiajing Wang,Satyanand Nalam,Sudhanshu Khanna,Geordie Braceras,Harold Pilo,Benton H. Calhoun +6 more
TL;DR: A margin/delay analysis of bias based circuit assist methods is presented, highlighting the assist impact on the functional metrics, margin and performance and a means of categorizing the assist methods are developed to provide a first order understanding of the underlying mechanisms.