Testing of on-chip RF and microwave circuits has always been a challenge to test engineers and has been more so in the recent past due to the high signal frequencies involved and the dense levels of circuit integration. In this paper, we propose to embed low-cost sensors into RF signal paths for the purpose of built-in test. The sensor characteristics are chosen in such a way that the sensor outputs, which are low frequency or DC signals, are tightly correlated with the target test specification values of the RF device-under-test. Hence, instead of testing the devices specifically for complex performance metrics (this is difficult for embedded circuits), the outputs of the sensors are used to accurately estimate the target test specification values when the device-under-test is stimulated with sinusoidal stimulus. This significantly impacts the cost of manufacturing test and allows testing to be performed using low-cost external testers. Using this method, the target test specification values can be estimated with an accuracy of /spl plusmn/5% of their actual value.

Use of embedded sensors for built-in-test RF circuits

Study on the improved fuzzy clustering algorithm and its application in brain image segmentation

A bias current topology with embodiments in current source, current reference, (pseudo bandgap) voltage reference, and bandgap voltage reference that operate at ultra low currents and low power supply voltages which may use main stream standard digital Complementary Metal-Oxide-Semiconductor (CMOS) processes. The bias current topology uses chiefly a self cascode (SC), whose active resistor MOSFET is paced in series with the gate input of the MOSFETs that help generate the proportional to absolute temperature (PTAT) voltage that is applied to the active resistor MOSFET to produce a bias current.

Ultra-low power bias current generation and utilization in current and voltage source and regulator devices

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.

/pdf/code-width-testing-based-compact-adc-bist-circuit-2yaeuvd639.pdf

Code-width testing-based compact ADC BIST circuit

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

A Fast and Adaptive PLL For Single Phase Grid-Connected PV Systems

This paper presents a linear high capture range clock and data recovery (CDR) system with adaptive loop gain in 180 nm CMOS. The high capture range of the CDR is achieved by a Hogge phase detector which exploits an adjustable strobe point that varies the control voltage to get locked. The loop bandwidth of the system varies automatically for better jitter transfer without jitter peaking increasement. The proposed system operates from 9 to 10.8 Gb/s and its loop bandwidth varies from 7.5 MHz to 2.7 MHz which improves jitter transfer by 11.87 dB. The random jitter of the recovered data is $\pmb{0.486 \ \mathbf{ps}_{\mathbf{rms}}}$ at BER of $\pmb{10^{-12}}$ .

A 9-10.8 Gb/s Linear Clock and Data Recovery System with Adaptive Loop Gain

This paper describes a new and novel subranging analog-to-digital converter based on parallel comparison and subtraction. A high-resolution and high-speed converter has been achieved as a result of elimination of input sample-and-hold circuit and by performing subtraction and comparison operation simultaneously. The converter performs a 3-bits conversion followed by standard flash conversion, for example of 8-bits. The first 3-bit cell has been designed elaborately in order to minimize the errors in an entire A/D converter. A high speed subtracter which employed an operational amplifier with 90-dB DC gain and 900 MHz gain-bandwidth (GBW) and high speed and low offset comparator which uses self calibrating technique are presented. These circuits are designed in 0.8 /spl mu/m BiCMOS technology. In our implementation, A/D converter operates at 1 MHz with signal-to-noise ratio of 62 dB. The nonlinearity errors, INL and DNL, are less than 1 LSB in an 11-bit A/D converter The results show the possibility of increasing the resolution of 3-bits for any converter. So, a pre-processing stage is proposed for the resolution enhancement. Therefore, the A/D converter with resolution more than 15-bits is possible with this technique.

A novel A/D converter for high-resolution and high-speed applications

: Power decoupling of pulsating grid side power from constant source side power is one of the paramount issues in single phase-phase grid-connected renewable systems. The principal aim of such systems is the decrease of the capacitance of the decoupled capacitor. However, this causes some problems such as an increase in the total harmonic distortion (THD) of injected current to the grid and bus voltage fluctuations. By considering the aforementioned explanation, utilizing control strategies is critical to modify system performance. The voltage controller is responsible for adjusting the bus voltage, suppressing the second-order harmonic, and providing a trade-off between system cost and total harmonic distortion as well as bus voltage fluctuations. This paper presents a digital notch filter in order to improve the system transient response and remove the harmonic ripples. The relations between system cost, THD, and bus voltage fluctuations have been described completely. Moreover, the mathematical expressions of the proposed digital notch filter have been provided. The analyzed system is 250 W PV panel connected to a 220 V RMS, 50 HZ grid. The THD of injected current to the grid is approximately 0.6%.

/pdf/design-of-a-digital-voltage-controller-in-single-phase-grid-3lu97l2j.pdf

Mehdi Ehsanian

Papers

A Fast and Adaptive PLL For Single Phase Grid-Connected PV Systems

A 9-10.8 Gb/s Linear Clock and Data Recovery System with Adaptive Loop Gain

A novel A/D converter for high-resolution and high-speed applications

Design of a Digital Voltage Controller in Single-Phase Grid-Connected Renewable Converters