An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.

Method of depositing an amorphous carbon layer

The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly, the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon, silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.

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Plasma etching: Yesterday, today, and tomorrow

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

Method for integrated circuit fabrication using pitch multiplication

A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.

Method for critical dimension shrink using conformal pecvd films

A method is provided for processing a substrate including treating a surface of a dielectric layer comprising silicon and carbon by exposing the dielectric layer comprising silicon and carbon to a plasma of an inert gas, and depositing a photoresist on the dielectric layer comprising silicon and carbon. The dielectric layer may comprise a first dielectric layer comprising silicon, carbon, and nitrogen, and a second layer of nitrogen-free silicon and carbon containing material in situ on the first dielectric layer, and a third dielectric layer comprising silicon, oxygen, and carbon on the second dielectric layer.

Method of eliminating photoresist poisoning in damascene applications

The invention provides methods and apparatuses for fabricating a dual damascene structure on a substrate First, trench lithography and trench patterning are performed on the surface of a substrate to etch a low-k dielectric material layer to a desired etch depth to form a trench prior to forming of a via The trenches can be filled with an organic fill material and a dielectric hard mask layer can be deposited Then, via lithography and via resist pattering are performed Thereafter, the dielectric hard mask and the organic fill material are sequentially etched to form vias on the surface of the substrate, where the trenches are protected by the organic fill material from being etched A bottom etch stop layer on the bottom of the vias is then etched and the organic fill material is striped As a result, the invention provides good patterned profiles of the via and trench openings of a dual damascene structure

Dual damascene fabrication with low k materials

A method of forming an interconnect structure comprising: forming a sacrificial inter-metal dielectric (IMD) layer over a substrate, wherein the sacrificial IMD layer comprising a carbon-based film, such as amorphous carbon, advanced patterning films, porous carbon, or any combination thereof; forming a plurality of metal interconnect lines within the sacrificial IMD layer; removing the sacrificial IMD layer, with an oxygen based reactive process; and depositing a non-conformal dielectric layer to form air gaps between the plurality of metal interconnect lines. The metal interconnect lines may comprise copper, aluminum, tantalum, tungsten, titanium, tantalum nitride, titanium nitride, tungsten nitride, or any combination thereof. Carbon-based films and patterned photoresist layers may be simultaneously removed with the same reactive process. Highly reactive hydrogen radicals processes may be used to remove the carbon-based film and simultaneously pre-clean the metal interconnect lines prior to the deposition of a conformal metal barrier liner.

Air gap interconnects using carbon-based films

A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer (302) upon a substrate (300), an etch stop layer (304) over the first insulator layer (302), and a second insulator layer (306) atop the etch stop layer (304). A via mask (308) is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer (302), the etch stop layer (304) and the second insulator layer (306) may be etched in a single step, for example, using a reactive ion etch. The hole (312) that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer (306). The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

Mehul Naik

Papers

Method for critical dimension shrink using conformal pecvd films

Method of eliminating photoresist poisoning in damascene applications

Dual damascene fabrication with low k materials

Air gap interconnects using carbon-based films

Method of producing an interconnect structure for an integrated circuit