Sturdy multi-stage noise-shaping (SMASH) delta-sigma modulators (DSMs) achieve high-order noise-shaping while significantly alleviating the mismatch issue between analog and digital transfer functions. Based on the SMASH architecture, we propose a methodology of synthesizing its continuous-time (CT) architecture from its discrete-time (DT) counterpart by using loop-filter connections. The proposed methodology circumvents the necessity of a direct extraction of the quantization noise from the early stages, which is problematic for CT architectures with high sampling rate. Moreover, the proposed method allows to intuitively compensate the CT SMASH for the excess loop delay (ELD). Furthermore, an input feedforward path is introduced into the second stage to eliminate the STF peaking induced by the ELD. A 2–2 SMASH topology is analyzed as a case study to demonstrate the synthesis methodology. Besides, we present derivations for determining loop-filter coefficients. Simulation results confirm the efficacy of the synthesis methodology for the SMASH topology.

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators

Sturdy multi-stage noise-shaping (SMASH) delta-sigma modulators (DSMs) achieve high-order noise-shaping while significantly alleviating the mismatch issue between analog and digital transfer functions. Based on the SMASH architecture, we propose a methodology of synthesizing its continuous-time (CT) architecture from its discrete-time (DT) counterpart by using loop-filter connections. The proposed methodology circumvents the necessity of a direct extraction of the quantization noise from the early stages, which is problematic for CT architectures with high sampling rate. Moreover, the proposed method allows to intuitively compensate the CT SMASH for the excess loop delay (ELD). Furthermore, an input feedforward path is introduced into the second stage to eliminate the STF peaking induced by the ELD. A 2–2 SMASH topology is analyzed as a case study to demonstrate the synthesis methodology. Besides, we present derivations for determining loop-filter coefficients. Simulation results confirm the efficacy of the synthesis methodology for the SMASH topology. 

In this paper the heuristic-search based design of Sigma-Delta modulators with FIR feedback is described. Using single-bit quantizers in Sigma-Delta modulators (SDMs) is very common due to their inherent linearity. However, their binary feedback increases the requirements for the integrators and the jitter sensitivity in the loop compared to multi-bit feedback. FIR feedback tries to resolve these problems, however, requires a second compensating FIR filter and an adjusted loopfilter scaling in order to restore the original noise transfer characteristic. This not only makes the design process more challenging but also leads to increased peaking of the STF, undesirable for many applications. Therefore, in this work a heuristic-search based design approach is presented which offloads work from the designer to an automated design environment. It allows to design CT SDMs directly in the CT domain including the compensation of nonidealities and STF engineering in order to counteract the peaking. The theoretical background is described as well as the additions to the underlying design framework. Alongside, design examples are given to illustrate the advantages of this approach.

Automated Design of Sigma-Delta Modulators with FIR Feedback

Excess loop delay (ELD) in high speed continuoustime (CT) Delta-Sigma-Modulators (DSMs) imposes design challenges and limits the use of high resolution, e.g. successiveapproximation-register (SAR) based internal quantizers, as usual compensation techniques like the use of a direct path around the quantizer come with increased swings and reduced maximum stable amplitude (MSA). In this paper, two bitwise ELD compensation approaches applicable to cascade-of-integrators with distributed feedback (CIFB) loop filters are proposed, which alleviate this problem for SAR and other multi-step quantizers by sequentially feeding bits into the feedback loop when they are available (MSB first, LSB last). Loop-filter equivalence for such bitwise ELD compensation is analytically derived. System-level simulations using Matlab & Simulink for exemplary 4-bit 2nd, 3rd and 4th-order modulators show 40% reduction of the last integrator output swing compared to the conventional direct path compensation. This potentially allows to avoid the swing, quantizer scaling and noise trade-offs due to ELD in state of the art designs.

Bitwise ELD Compensation in Δ∑ Modulators

A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback

This paper analyzes the effect of signal transfer function (STF) peaking in continuous-time (CT) Delta-Sigma- Modulators (DSMs) arising from excess loop delay (ELD) and its compensation. Starting from a generic model, the origin of different contributors to STF peaking are revised, namely noise transfer function (NTF) peaking due to aggressive noise shaping, instability from uncompensated delay as well as forward loop filter zeros in cascade-of-integrators with distributed feedforward (CIFF) modulators. The shift of forward loop filter zeros as a result of ELD compensation is shown intuitively for a 3rd order example, while system-level simulations of various 2nd, 3rd and 4th order CT single-loop modulators confirm increased STF peaking in the above stated scenarios.

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators

The performance of a 0-X MASH DSM is primarily defined by the DSM noise-shaping and the inter-stage gain (ISG). Due to system specification like modulator order and OSR, the DSM noise shaping is limited. All further performance in the 0-X MASH modulator is achieved by setting a large ISG, which amplifies the residue signal before it is processed by the fine stage DSM. This paper presents an analysis of the factors influencing the ISG and proposes measures, which can be used to maximize it. Most importantly, it is shown, that the CIFB DSM architecture is preferred, since the wideband residue overloads the CIFF architecture with its peaking OOB STF much earlier, thus CIFB results in more ISG and less internal swings. The presented analysis can be used as a guideline for achieving optimum performance in a 0-X MASH DSM and yielding the maximum SQNR.

Michael Pietzko

Papers

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators

Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators

Bitwise ELD Compensation in Δ∑ Modulators