In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

Incremental Delta-Sigma ADCs: A Tutorial Review

In this paper, a comparison between three different current readouts for micro-potentiostats is presented: resistive transimpedance amplifier (R-TIA), capacitive transimpedance amplifier (C-TIA), and current-mode continuous-time sigma-delta modulator (Current-CTSDM). The comparison is carried out on the signal transfer function, the required amplifier gain-bandwidth (GBW), its input referred noise current, required area and power, and dynamic range. Each approach and its limitations are separately discussed. The three systems have been simulated using VerilogA models and the results are compared. It is shown that each system comes with its own limitations, however current-mode CTSDM are more beneficial due to their intrinsic digitization.

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Comparison Study of Integrated Potentiostats: Resistive-TIA, Capacitive-TIA, CT ΣΔ Modulator

In this brief, the calculation of the signal behavior and the achievable signal-to-quantization-noise ratio of continuous-time (CT) incremental sigma–delta (I-SD) analog-to-digital converters (ADCs) is described. The presented method allows for the analysis of I-SD ADCs in frequency domain, including the specific non-idealities of the CT modulator. In the state-of-the-art, it is described that the omission of the preceding sample-and-hold for the I-SD ADC alters the transfer characteristic compared to a Nyquist-rate converter. So far, for CT I-SD ADCs this behavior is only investigated via simulations. In this brief, the model of a discrete-time I-SD ADC is generalized and adapted for the CT case. This allows to analytically obtain the signal and noise transfer function of the I-SD ADC in frequency domain in combination with arbitrary reconstruction filters due to the utilization of the lifting method in a fast and accurate way.

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On the Signal Filtering Property of CT Incremental Sigma–Delta ADCs

This paper presents a delta-sigma modulation control scheme for buck converters that features a reconfigurable loop filter with a scalable sampling frequency for effective switching noise reduction and high conversion efficiency. Depending on the load current, the proposed controller changes the sampling frequency along with the delta-sigma modulator (DSM) structure to transform between third- and second-order loop filters. Thus, it maintains a robust noise shaping capability and reduces the power consumption over a wide load range. The loop filters are implemented with a single op-amp resonator to reduce multiple integrators into a single element and enhance controllability of the resonance. More power-efficient operation is obtained by a switching node assisted deadtime controller (SADTC) that regulates the body-diode conduction. The proposed DSM-based buck converter was fabricated on a 180 nm CMOS. A spurious-free output spectrum with a noise floor below −81 dBm was achieved across all sampling frequencies. It operated at a wide range sampling frequencies of 3.75–15 MHz and regulated the output in the range of 1.0–2.4 V with input voltages of 2.5–5.5 V. The output voltage ripples were maintained under 19 mV. The converter showed a conversion efficiency of better than 80% over a load range of 1–1000 mA with a peak efficiency of 95.4% at 125 mA.

A Low Switching Noise and High-Efficiency Buck Converter Using a Continuous-Time Reconfigurable Delta-Sigma Modulator

This paper reports on a low-power readout IC (ROIC) for high-fidelity recording of the photoplethysmogram (PPG) signal. The system comprises a highly reconfigurable, continuous-time, second-order, incremental delta-sigma modulator (I–ΔΣM) as a light-to-digital converter (LDC), a 2-channel 10b light-emitting diode (LED) driver, and an integrated digital signal processing (DSP) unit. The LDC operation in intermittent conversion phases coupled with digital assistance by the DSP unit allow signal-aware, on-the-fly cancellation of the dc and ambient light-induced components of the photodiode current for more efficient use of the full-scale input range for recording of the small-amplitude, ac, PPG signal. Fabricated in TSMC 0.18 μm 1P/6M CMOS, the PPG ROIC exhibits a high dynamic range of 108.2 dB and dissipates on average 15.7 μW from 1.5 V in the LDC and 264 μW from 2.5 V in one LED (and its driver), while operating at a pulse repetition frequency of 250 Hz and 3.2% duty cycling. The overall functionality of the ROIC is also demonstrated by high-fidelity recording of the PPG signal from a human subject fingertip in the presence of both natural light and indoor light sources of 60 Hz.

A 280 μW, 108 dB DR PPG-Readout IC With Reconfigurable, 2nd-Order, Incremental ΔΣM Front-End for Direct Light-to-Digital Conversion

This paper presents a straightforward method of STF engineering in continuous-time ΣΔ modulators within the web-based design tool www.sigma-delta.de. There are already different well known methods to obtain the STF depending on constraints given by the designer. One possibility is the analytical derivation of the high-level coefficients yielding a certain STF. Further, the ΣΔ modulator can be embedded into a filter with the desired characteristic or vice versa. However, as the NTF and STF are dependent upon each other, they cannot be chosen independently. The web-based design tool for continuous-time ΣΔ modulators relies on a heuristic search based on a genetic algorithm that is able to determine a STF complying to given constraints while maximizing the signal-to-noise ratio of the chosen modulator architecture at the same time. This paper shows the capabilities of the publicly available design tool in regard of STF engineering and gives corresponding examples.

STF engineering in CT sigma-delta modulators using www.sigma-delta.de

This paper presents a dynamic power reduction technique for incremental $\Delta \Sigma $ (I- $\Delta \Sigma $ ) modulators. The technique makes use of the unequal weighting of the digital reconstruction filter. The underlying idea is that the input signal samples are not equally weighted in the higher order reconstruction filter. Thus, it is possible to increase the non-idealities of the I- $\Delta \Sigma $ modulator during the runtime of a single Nyquist conversion, thereby saving power. This principal idea is verified by an example design, where the input-referred noise of the first integrator is dynamically increased, which allows for improved efficiency. The proposed technique is readily applicable to every state-of-the-art I- $\Delta \Sigma $ modulator. Furthermore, it is shown that this property can also be used to switch a single-bit digital-to-analog converter (DAC) into a multibit DAC during runtime, thereby greatly improving the achievable signal-to-quantization-noise ratio (SQNR) without suffering from the DAC non-linearity. The prototype I- $\Delta \Sigma $ modulator is manufactured in a 180-nm CMOS technology and achieves a dynamic range/SNDR = 91.5/86.6 dB for a sampling rate of 200 kS/s while consuming l.l mW from a 3-V supply, while the dynamic power reduction method accounts for 30% power savings.

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A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators

This paper analyzes the effect of signal transfer function (STF) peaking in continuous-time (CT) Delta-Sigma- Modulators (DSMs) arising from excess loop delay (ELD) and its compensation. Starting from a generic model, the origin of different contributors to STF peaking are revised, namely noise transfer function (NTF) peaking due to aggressive noise shaping, instability from uncompensated delay as well as forward loop filter zeros in cascade-of-integrators with distributed feedforward (CIFF) modulators. The shift of forward loop filter zeros as a result of ELD compensation is shown intuitively for a 3rd order example, while system-level simulations of various 2nd, 3rd and 4th order CT single-loop modulators confirm increased STF peaking in the above stated scenarios.

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators

In a successive-approximation-register (SAR) ADC, comparator noise is often one of the dominant error sources. In this brief, the relation between the input referred noise of a comparator and its resulting noise in an SAR ADC is presented. A scaling factor less than unity is found when the comparator noise is referred back to the ADC input. When the comparator contains both thermal and flicker noise, the noise profile is maintained when referred back to the ADC input; however, due to aliasing caused by sampling, the flicker noise corner at the ADC output is pushed toward lower frequencies compared with the flicker noise corner frequency of the comparator. The results are analytically derived and proven by simulation and measurement.

Johannes Wagner

Papers

On the Signal Filtering Property of CT Incremental Sigma–Delta ADCs

STF engineering in CT sigma-delta modulators using www.sigma-delta.de

A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators

Input Referred Comparator Noise in SAR ADCs