http://ieeexplore.ieee.org/iel5/5/31324/01456901.pdf

Microelectronic circuits

This paper presents a power and area efficient digital communication interface for tiny distributed direct digitizing neural recorder ASICs on an ultra-flexible neural implant in a bus-like structure in order to realize a NeuroBus. The digital interface only requires 3 pins, does not need any preprogramming or trimming for address allocation and achieves a very low core area. The digital interface was implemented in a 1.2V 180nm CMOS technology and supports up to 100 spatially distributed neural recorder ASICs, consuming only $9\ \mu\mathrm{W}$ of power per channel on a tiny area of $2380\ \mu\mathrm{m}^{2}$.

NeuroBus – Architecture and Communication Bus for an Ultra-Flexible Neural Interface

Incremental delta-sigma analog-to-digital converters (IADC) are widely used in modern high-fidelity audio, sensors, and 1oT low-power applications. Over the past years, the techniques to implement high-resolution lADCs have been significantly improved, (a) for example, in handling the weighting problems inside the lADCs to overcome thermal noise and DAC mismatch issues. This paper offers a tutorial review on the considerations of weightings in lADCs. The influence of weightings on thermal noise and DAC mismatches is analyzed, and the use of weighting in algorithms is described specifically. The advanced architectures to take advantage of the weightings based on recent academic achievements are presented respectively, with design examples to illustrate the successful practical implementations.

Weightings in Incremental ADCs: A Tutorial Review

This work presents a calibration-free 96.7 dB SNDR 4 MS/s third order Continuous-Time Incremental Sigma-Delta modulator (CT I-SDM). The design relies on open-loop integrators leading to a capacitive input of 987 fF easing the design of driving stages. The performance is achieved through the use of a resistive multi bit feedback DAC employing a modified dynamic element matching scheme and supply current compensation to reduce distortion. Further, chopping is used to reduce the impact of flicker noise in the loop filter. The clock jitter requirements of the ADC are relaxed through the use of finite impulse response (FIR) feedback in combination with a 5 bit internal SAR ADC. The design is implemented in a 22 nm FDSOI technology consuming an area of 0.25 mm2.

A Calibration-Free 96.7 dB SNDR 4 MS/s CT I-SD Modulator With Single Feedback DAC

Demands for neural interfaces around functionality, high spatial resolution, and longevity have recently increased. These requirements can be met with sophisticated silicon-based integrated circuits. Embedding miniaturized dice in flexible polymer substrates significantly improves their adaptation to the mechanical environment in the body, thus improving the systems' structural biocompatibility and ability to cover larger areas of the brain. This work addresses the main challenges in developing a hybrid chip-in-foil neural implant. Assessments considered (1) the mechanical compliance to the recipient tissue that allows a long-term application and (2) the suitable design that allows the implant's scaling and modular adaptation of chip arrangement. Finite element model studies were performed to identify design rules regarding die geometry, interconnect routing, and positions for contact pads on dice. Providing edge fillets in the die base shape proved an effective measure to improve die-substrate integrity and increase the area available for contact pads. Furthermore, routing of interconnects in the immediate vicinity of die corners should be avoided, as the substrate in these areas is prone to mechanical stress concentration. Contact pads on dice should be placed with a clearance from the die rim to avoid delamination when the implant conforms to a curvilinear body. A microfabrication process was developed to transfer, align, and electrically interconnect multiple dice into conformable polyimide-based substrates. The process enabled arbitrary die shape and size over independent target positions on the conformable substrate based on the die position on the fabrication wafer. 

/pdf/highly-conformable-chip-in-foil-implants-for-neural-2dl4lva2.pdf

Highly conformable chip-in-foil implants for neural applications

This article shows the design of a wideband 3-0 sturdy-multi-stage noise-shaping (SMASH) continuous-time (CT) incremental delta–sigma (I- $\boldsymbol {\Delta \Sigma }$ ) analog-to-digital converter (ADC). The two stages’ quantizers (QTZs) are implemented by a single re-configurable multibit (MB) asynchronous (A)SAR ADC. The digital-to-analog converter (DAC) nonlinearities are suppressed by reconfiguring the asynchronous successive-approximation register (ASAR) ADC from 2 to 5 b, and correspondingly, the DACs dynamically switch from 1.5- to 4-b tri-level outputs within each Nyquist conversion cycle. This results in a DAC-calibration-free MB operation. A two-tap FIR filter is implemented in the feedback DACs to reduce jitter requirements in the initial 1.5-b cycles. Through the design representation, a detailed fundamental comparison between an X-0 SMASH architecture and an X-order single-loop modulator is discussed. This discussion highlights the introduction of an efficient tri-level combination between the MSB and the LSBs of the ASAR QTZ. The resulting SMASH CT I- $\boldsymbol {\Delta \Sigma }$ modulator was fabricated in 28-nm CMOS technology with an active area of 0.125 mm2. It achieves 97-dB spurious-free dynamic range (SFDR) without calibration, 89-dB dynamic range (DR), and 81.2-dB SNDR in a 1-MHz bandwidth (BW). It consumes 3.6 mW from a single 0.9-V supply. The design shows very good robustness across different tested samples, supply variations, and across temperatures from −20 °C to 80 °C.

A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS

This article presents a direct digitizing neural recorder that uses a body-induced offset based DC servo loop to cancel electrode offset (EDO) on-chip. The bulk of the input pair is used to create an offset, counteracting the EDO. The architecture does not require AC coupling capacitors which enables the use of chopping without impedance boosting while maintaining a large input impedance of 238 M<inline-formula><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> over the whole 10 kHz bandwidth. Implemented in a 180 nm HV-CMOS process, the prototype occupies a silicon area of only 0.02 mm<sup>2</sup> while consuming 12.8 μW and achieving 1.82 μV<inline-formula><tex-math notation="LaTeX">$_{\text{rms}}$</tex-math></inline-formula> of input-referred noise in the local field potential (LFP) band and a NEF of 5.75.

A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop

This paper presents a modified Look-Up-Table (LUT) based DAC foreground calibration for multi-bit continuous-time Delta-Sigma Modulators. The feedback DAC in DSMs is usually a performance bottleneck, as all of its errors directly add at the input node. Fore - or background error correction based on LUT can efficiently eliminate the DAC errors, but can also impose significant circuit overhead in the digital and analog domain. The presented method reduces the correction complexity while maintaining the same performance as current state-of-the-art solutions towards static and dynamic errors.

Complexity Reduced LUT-Based DAC Correction in Continuous-Time Delta-Sigma Modulators

Magnetic Resonance Imaging (MRI) is a non-invasive procedure used in the medical community as a powerful way of creating images of the human anatomy. MRI is preferred over other examination techniques such as X-ray computed tomography (CT) because of its excellent soft tissue discrimination as well as the absence of ionizing radiation. Currently most clinical MRI systems use the single radio frequency coil imaging. However over past several years research has increasingly focused on the concept of using arrays of mutually decoupled surface coils. These surface coil arrays can simultaneously acquire multiple images, resulting in an increase in the field of view. This thesis pursues the design and construction of a high impedance preamplifier with the goal of investigating the decoupling of a surface coil array in a 4.7T magnetic resonance system.

Design of a High Impedance Preamplifier for Coil Arrays

The performance of a 0-X MASH DSM is primarily defined by the DSM noise-shaping and the inter-stage gain (ISG). Due to system specification like modulator order and OSR, the DSM noise shaping is limited. All further performance in the 0-X MASH modulator is achieved by setting a large ISG, which amplifies the residue signal before it is processed by the fine stage DSM. This paper presents an analysis of the factors influencing the ISG and proposes measures, which can be used to maximize it. Most importantly, it is shown, that the CIFB DSM architecture is preferred, since the wideband residue overloads the CIFF architecture with its peaking OOB STF much earlier, thus CIFB results in more ISG and less internal swings. The presented analysis can be used as a guideline for achieving optimum performance in a 0-X MASH DSM and yielding the maximum SQNR.

John Gabriel Kauffman

Papers

A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS

A Direct Digitizing Chopped Neural Recorder Using a Body-Induced Offset Based DC Servo Loop

Complexity Reduced LUT-Based DAC Correction in Continuous-Time Delta-Sigma Modulators

Design of a High Impedance Preamplifier for Coil Arrays

Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators