Cyber-Physical Systems (CPS) are integrations of computation and physical processes. Embedded computers and networks monitor and control the physical processes, usually with feedback loops where physical processes affect computations and vice versa. The economic and societal potential of such systems is vastly greater than what has been realized, and major investments are being made worldwide to develop the technology. There are considerable challenges, particularly because the physical components of such systems introduce safety and reliability requirements qualitatively different from those in general- purpose computing. Moreover, physical components are qualitatively different from object-oriented software components. Standard abstractions based on method calls and threads do not work. This paper examines the challenges in designing such systems, and in particular raises the question of whether today's computing and networking technologies provide an adequate foundation for CPS. It concludes that it will not be sufficient to improve design processes, raise the level of abstraction, or verify (formally or otherwise) designs that are built on today's abstractions. To realize the full potential of CPS, we will have to rebuild computing and networking abstractions. These abstractions will have to embrace physical dynamics and computation in a unified way.

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Cyber Physical Systems: Design Challenges

This paper describes the ATLAS experiment as installed in i ts experimental cavern at point 1 at CERN. It also presents a brief overview of the expec ted performance of the detector.

http://absimage.aps.org/image/SES08/MWS_SES08-2008-020010.pdf

The ATLAS Experiment at the CERN Large Hadron Collider

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.

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Reconfigurable computing: a survey of systems and software

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

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Garp: a MIPS processor with a reconfigurable coprocessor

This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems.

MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space.

A dynamic instruction set computer

In this paper, we argue that model-based design and platform-based design are two views of the same thing. A platform is an abstraction layer in the design flow. For example, a core-based architecture and an instruction set architecture are platforms. We focus on the set of designs induced by this abstraction layer. For example, the set of all ASICs based on a particular core-based architecture and the set of all x86 programs are induced sets. Hence, a platform is equivalently a set of designs. Model-based design is about using platforms with useful modeling properties to specify designs, and then synthesizing implementations from these specifications. Hence model-based design is the view from above (more abstract, closer to the problem domain) and platform-based design is the view from below (less abstract, closer to the implementation technology). One way to define a platform is to provide a design language. Any valid expression in the language is an element of the set. A platform provides a set of cons...

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Actor-oriented design of embedded hardware and software systems

This paper describes an efficient approach of applying mitigation to an FPGA design to protect against Single Event Upsets (SEUs). This approach applies mitigation selectively to FPGA circuit structures depending on their importance within the design. Higher priority is given to structures causing "persistent" errors within the design. For certain applications, applying selective mitigation to the persistent components can yield higher returns in reliability per unit cost than full mitigation. A software tool is also introduced which automatically classifies circuit structures based on this concept and applies Triple Modular Redundancy (TMR) selectively based on the classification of the circuit structure.

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Improving FPGA Design Robustness with Partial TMR

Reconfigurable logic systems approach the performance of application-specific integrated circuits (ASICs) while retaining much of the generality of conventional computing systems through reconfiguration. Unfortunately, the development of these systems, unlike conventional software systems, is hardware-intensive, requiring significant hardware development time. One way to introduce a more flexible development approach is to implement a customizable stored-program processor. For a given application, the designer can develop customized hardware to increase performance and then control the sequencing and operation of this hardware with software. Development time can be significantly reduced because conventional software development tools, e.g. assemblers and compilers, can be used to quickly develop new applications on the customized processor. This paper presents the Nano Processor, a fully customizable reconfigurable processor, together with its integrated assembler, that has been successfully implemented on the Xilinx 3000 series field programmable gate array (FPGA). >

The Nano Processor: a low resource reconfigurable processor

SRAM-based FPGA devices are susceptible to single event effects (SEE) including single event upsets (SEU) within the configuration memory. Configuration scrubbing along with TMR or other hardware redundancy techniques are often used to mitigate the effects of these SEUs. However, the use of traditional configuration scrubbing prevents the ability to reconfigure the FPGA dynamically or to perform partial reconfiguration. This paper presents a novel technique that allows partial reconfiguration to be used with configuration scrubbing. A self scrubber, utilizing a small portion of the FPGA, performs the necessary operations to reconfigure a portion of the design while continuously scrubbing the entire FPGA.

Michael Wirthlin

Papers

A dynamic instruction set computer

Actor-oriented design of embedded hardware and software systems

Improving FPGA Design Robustness with Partial TMR

The Nano Processor: a low resource reconfigurable processor

FPGA partial reconfiguration via configuration scrubbing