An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

/pdf/active-pixel-sensor-with-intra-pixel-charge-transfer-387ug1605r.pdf

Active pixel sensor with intra-pixel charge transfer

Single substrate device is formed to have an image acquistition device and a controller. The controller on the substrate controls the system operation.

/pdf/cmos-active-pixel-sensor-type-imaging-system-on-a-chip-1pw7w4xxhm.pdf

CMOS active pixel sensor type imaging system on a chip

An electro-optical device having a plurality of pixels including a plurality of EL elements, wherein the electro-optical device provides a gray scale display by controlling a period of time at which the plurality of the EL elements emit light in one frame period; the plurality of the EL elements have a first electrode and a second electrode; the first electrode is held at a constant potential; and a potential of the second electrode changes in such a manner that a polarity of an EL driving voltage, which is a difference between the potentials applied to the first and second electrodes, is inverted for each one frame period.

Electro-optical device

A thin film MOS transistor has a construction which can minimize scattering of electron and thus maximize electrons mobility for allowing higher speed operation of the transistor. For this, the MOS transistor has a thin film semiconductor layer having a thickness in a range less than or equal to 100 nm, between a pair of gate electrodes which oppose each other across the semiconductor layer.

Thin film MOS transistor having pair of gate electrodes opposing across semiconductor layer

The image area of the frame FIT (frame-interline-transfer)-CCD (charge-coupled-device) image sensor is 140 mm (H)*79 mm (V), the effective number of pixels is 1920 (H)*1036 (V) and the unit cell size of a pixel is 73 mu m (H)*76 mu m (V) These specifications are for the high-definition-television (HDTV) format The horizontal shift register consists of dual-channel, two-phase CCDs driven by a 37125-MHz clock pulse The readout phase of each channel is the same, which allows the reset gate of each channel to be connected together To adapt to the 7425-MHz readout frequency, one of the output signals is delayed by 1347 ns through a sample-hold circuit To reduce the voltage drop of the vertical shift register (V-CCD) drive pulse along the poly-Si transfer gate, an Al wire is put onto the transfer gate and interconnected to decrease the resistance This Al wire works also as a photoshield In addition, another poly-Si layer placed between the Al wire and the transfer gate prevents potential shift by separating the poly-Si contact of the transfer gate/poly-Si layer, from the Al contact of the poly-Si layer/Al wire >

A 2 million pixel FIT-CCD image sensor for HDTV camera system

A 1-in optical format frame-interline-transfer charge-coupled-device (FIT-CCD) image sensor with 2 million pixels and an aspect ratio of 16(H):9(V) has been developed for HDTV cameras. The effective number of pixels is 1920(H)*1036(V). In order to decrease the smear level, achieve uniform charge handling capability for the vertical CCD, and eliminate defects that appear as vertical stripes in the image of the device, aluminum wire was put onto the vertical transfer gate to decrease the resistance in the transfer gate and a dual-channel two-phase CCD was utilized for the horizontal shift register operated by a 37.125-MHz clock. As a result, this image sensor has a dynamic range of 72 dB and a sensitivity of 75 nA/lx for light with a color temperature of 2856 K. Smear is reduced to -100 dB by using the FIT-CCD image sensor structure. The horizontal limit is 1000 TV lines. In addition, image lag is negligibly small and below the sensitivity of the measurement instrument. >

A 2 million pixel FIT-CCD image sensor for HDTV camera systems

A 2/3-in optical format CCD (charge-coupled device) image sensor for HDTV (high-definition television) cameras is described. The image area is 9.6 (H)*5.4 (V)mm/sup 2/, the effective number of pixels is 1920 (H)*1036 (V), and the unit cell size is 5.0 (H)*5.2 (V) mu /sup 2/. Dual-channel horizontal registers (H-CCDs) are adopted. The barrier potential area is formed under the signal partitioning transfer gate between the dual H-CCDs. The smear drain for sweeping smear charges away is arranged alongside the second H-CCD. The n+ regions in the smear drain are separated. The frame shift frequency should be raised as high as possible to reduce the smear level. On the other hand, the frame shift frequency is limited by the drive capability. In this context, the frequency is set to 1.5 MHz. >

A 2/3-inch 2 M pixel FIT-CCD HDTV image sensor

A CCD imager wherein signal charge can be transferred at a high speed and smears can be minimized without employing a complicated wiring configuration. The CCD imager comprises a transfer electrode formed from a semiconductor layer, a light intercepting film formed from a first layer metal film on the transfer electrode, and a shunt wiring film formed from a second layer metal film on the first layer metal film. The transfer electrode and the shunt wiring film are electrically connected to each other by way of the light intercepting film. Also an improved CCD imager of the frame interline type is disclosed wherein a storage section is improved in light intercepting performance to prevent possible occurrence of smears at the storage section with a simplified configuration of wiring in the storage section.

Michio Negishi

Papers

Thin film MOS transistor having pair of gate electrodes opposing across semiconductor layer

A 2 million pixel FIT-CCD image sensor for HDTV camera system

A 2 million pixel FIT-CCD image sensor for HDTV camera systems

A 2/3-inch 2 M pixel FIT-CCD HDTV image sensor

Smear supressing CCD imager